ZHCSEV0 March 2016 DS90UB921-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings - JEDEC
- 6.3 ESD Ratings—IEC and ISO
- 6.4 Recommended Operating Conditions
- 6.5 Thermal Information
- 6.6 DC Electrical Characteristics
- 6.7 AC Electrical Characteristics
- 6.8 PCLK Timing Requirements
- 6.9 Recommended Timing for the Serial Control Bus
- 6.10 Switching Characteristics
- 6.11 Typical Charateristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 High Speed Forward Channel Data Transfer
- 7.3.2 Low Speed Back Channel Data Transfer
- 7.3.3 Common Mode Filter Pin (CMF)
- 7.3.4 Video Control Signal Filter
- 7.3.5 EMI Reduction Features
- 7.3.6 LVCMOS VDDIO Option
- 7.3.7 Power Down (PDB)
- 7.3.8 Remote Auto Power-Down Mode
- 7.3.9 Input PCLK Loss Detect
- 7.3.10 Serial Link Fault Detect
- 7.3.11 Pixel Clock Edge Select (TRFB)
- 7.3.12 Frequency Mode Optimizations
- 7.3.13 Interrupt Pins - Funtional Description and Usage (INTB, REM_INTB)
- 7.3.14 Internal Pattern Generation
- 7.3.15 GPIO[3:0] and GPO_REG[7:4]
- 7.3.16 I2S Transmitting
- 7.3.17 Built In Self Test (BIST)
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
5 Pin Configuration and Functions
DS90UB921-Q1
48 Pin WQFN (RHS)
Top View
Pin Functions
| PIN | I/O, TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NUMBER | ||
| LVCMOS PARALLEL INTERFACE - Layout note: for unused LVCMOS input pins, tie to an external pulldown | |||
| DIN[23:18], DIN[15:10], DIN[7:2] / R[7:2], G[7:2], B[7:2] | 27, 28, 29, 32, 33, 34, 37, 38, 39, 40, 41, 42, 45, 46, 47, 48, 1, 2 | I, LVCMOS, PD | Parallel Interface Data Input Pins |
| DIN[1:0], DIN[9:8], DIN[17:16] / R[1:0], G[1:0], B[1:0] | 25, 26, 35, 36, 43, 44 | Multi-function pin I/O, LVCMOS, PD |
Parallel Interface Data Input Pins DIN0 / R0 can optionally be used as GPIO0 and DIN1 / R1 can optionally be used as GPIO1 DIN8 / G0 can optionally be used as GPIO2 and DIN9 /G1 can optionally be used as GPIO3 DIN16 / B0 can optionally be used as GPO_REG4 and DIN17 / B1 can optionally be used as GPO_REG5 |
| HS | 3 | I, LVCMOS, PD | Horizontal Sync Input Pin Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs. See Video Control Signal Filter. |
| VS | 4 | I, LVCMOS, PD | Vertical Sync Input Pin Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130 PCLKs. See Video Control Signal Filter. |
| DE | 5 | I, LVCMOS, PD | Data Enable Input Pin Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs. See Video Control Signal Filter. |
| PCLK | 10 | I, LVCMOS, PD | Pixel Clock Input Pin. Strobe edge set by TRFB configuration register. See Table 7 0x03[0]. |
| I2S_CLK, I2S_WC, I2S_DA | 13, 12, 11 | Multi-function pin I, LVCMOS, PD |
Digital Audio Interface Data Input Pins Leave open if unused I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as GPO_REG7, and I2S_DA can optionally be used as GPO_REG6. |
| OPTIONAL PARALLEL INTERFACE - Layout note: for unused interface pins, tie to an external pulldown | |||
| GPIO[3:0] | 36, 35, 26, 25 | Multi-function pin I/O, LVCMOS, PD |
General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin or configuration register. See Table 7 0x0D - 0x0F. Leave open if unused. Shared with DIN9, DIN8, DIN1 and DIN0 |
| GPO_REG[7:4] | 12, 11, 44, 43 | Multi-function pin O, LVCMOS, PD |
General Purpose Outputs and set by configuration register. See Table 7 0x0F - 0x11. Share with I2S_WC, I2S_DA, or DIN17, DIN16. |
| CONTROL | |||
| PDB | 21 | I, LVCMOS, PD | Power-down Mode Input Pin PDB = H, device is enabled (normal operation) Refer to Power Up Requirements and PDB Pin section. PDB = L, device is powered down. When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is shutdown, and IDD is minimized. Control Registers are RESET. |
| MODE_SEL | 24 | S | Device Configuration Select. See Table 5. |
| FSEL | 15 | I, LVCMOS, PU | Frequency Mode Select. Enables Intermediate Frequency mode for coaxial operation. See Frequency Mode Optimizations. |
| I2C | |||
| IDx | 6 | S | I2C Serial Control Bus Device ID Address Select External pull-up to VDD33 is required under all conditions, DO NOT FLOAT. Connect to external pull-up and pull-down resistor to create a voltage divider. See Table 6. |
| SCL | 8 | I/O, Open Drain | I2C Clock Input / Output Interface Must have an external pull-up to VDD33, DO NOT FLOAT. Recommended pull-up: 4.7kΩ. |
| SDA | 9 | I/O, Open Drain | I2C Data Input / Output Interface Must have an external pull-up to VDD33, DO NOT FLOAT. Recommended pull-up: 4.7kΩ. |
| STATUS - Layout note: for unused interface pins, leave as No Connect | |||
| INTB | 31 | O, Open Drain | Interrupt INTB = H, normal INTB = L, Interrupt request Typically connected with 4.7kΩ to VDDIO. |
| REM_INTB | 16 | O, LVCMOS, PD | Interrupt. Mirrors status of INTB_IN from the remote deserializer. Note: REM_INTB will be driven LOW until lock is achieved with the downstream deserializer. REM_INTB = H, normal REM_INTB = L, interrupt request |
| FPD-LINK III SERIAL INTERFACE | |||
| DOUT+ | 20 | O, LVDS | True Output The output must be AC-coupled per the typical connection diagram. |
| DOUT- | 19 | O, LVDS | Inverting Output The output must be AC-coupled per the typical connection diagram. |
| CMF | 23 | CAP | Common Mode Filter. Typically connected with 0.1µF to GND |
| POWER AND GROUND (1) | |||
| VDD33 | 22 | Power | Power to on-chip regulator 3.0 V - 3.6 V. Typically connected with 4.7 uF to GND |
| VDDIO | 30 | Power | LVCMOS I/O Power 1.71 V - 1.89 V OR 3.0 V - 3.6 V. Typically connected with 4.7 uF to GND |
| GND | DAP | Ground | DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias. |
| REGULATOR CAPACITOR | |||
| CAPHS12, CAPP12 | 17, 14 | CAP | Decoupling capacitor connection for on-chip regulator. Typically connected with 4.7uF to GND at each CAP pin. |
| CAPL12 | 7 | CAP | Decoupling capacitor connection for on-chip regulator. Typically connected with two 4.7uF to GND at this CAP pin. |
| OTHERS | |||
| RES1 | 18 | GND | Reserved. Tie to Ground. |
(1) The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.
The definitions below define the functionality of the I/O cells for each pin. I/O TYPE:
- CAP = Capacitor connection
- LVCMOS = LVCMOS pin; Referenced to VDDIO IO supply
- I = Input
- O = Output
- I/O = Input/Output
- S = Strap pin. All strap pins have weak internal pull-ups or pull-downs. If the default strap value is needed to be changed then an external resistor should be used.
- PD, PU = Weak Internal Pull-Down/Pull-Up
- Multi-function pin