ZHCSQB6 September 2022 DS320PR822
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Secondary Mode | ||||||
| tSP | Pulse width of spikes which must be suppressed by the input filter |
50 | ns | |||
| tHD-STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated |
0.6 | μs | |||
| tLOW | LOW period of the SCL clock | 1.3 | μs | |||
| THIGH | HIGH period of the SCL clock | 0.6 | μs | |||
| tSU-STA | Set-up time for a repeated START condition |
0.6 | μs | |||
| tHD-DAT | Data hold time | 0 | μs | |||
| TSU-DAT | Data setup time | 0.1 | μs | |||
| tr | Rise time of both SDA and SCL signals | Pull-up resistor = 4.7 kΩ, Cb = 10 pF | 120 | ns | ||
| tf | Fall time of both SDA and SCL signals | Pull-up resistor = 4.7 kΩ, Cb = 10 pF | 2 | ns | ||
| tSU-STO | Set-up time for STOP condition | 0.6 | μs | |||
| tBUF | Bus free time between a STOP and START condition |
1.3 | μs | |||
| tVD-DAT | Data valid time | 0.9 | μs | |||
| tVD-ACK | Data valid acknowledge time | 0.9 | μs | |||
| Cb | Capacitive load for each bus line | 400 | pF | |||
| Primary Mode | ||||||
| fSCL-M | SCL clock frequency | 303 | kHz | |||
| tLOW-M | SCL low period | 1.90 | μs | |||
| THIGH-M | SCL high period | 1.40 | μs | |||
| tSU-STA-M | Set-up time for a repeated START condition |
2 | μs | |||
| tHD-STA-M | Hold time (repeated) START condition. After this period, the first clock pulse is generated |
1.5 | μs | |||
| TSU-DAT-M | Data setup time | 1.4 | μs | |||
| tHD-DAT-M | Data hold time | 0.5 | μs | |||
| tR-M | Rise time of both SDA and SCL signals | Pull-up resistor = 4.7 kΩ, Cb = 10 pF | 120 | ns | ||
| TF-M | Fall time of both SDA and SCL signals | Pull-up resistor = 4.7 kΩ, Cb = 10 pF | 2 | ns | ||
| tSU-STO-M | Stop condition setup time | 1.5 | μs | |||
| EEPROM Timing | ||||||
| TEEPROM | EEPROM configuration load time | Time to assert ALL_DONE_N after READ_EN_N has been asserted. | 7.5 | ms | ||
| TPOR | Time to first SMBus access | Power supply stable after initial ramp. Includes initial power-on reset time. | 50 | ms | ||