ZHCSQB6 September 2022 DS320PR822
PRODUCTION DATA
The DS320PR822 deploys an Rx detect state machine that governs the Rx detection cycle as defined in the PCI express specifications. At power up or after a manual PD0/1 or SEL1/0 toggle the redriver determines whether or not a valid PCI express termination is present at the far end receiver. The RX_DET pin of DS320PR822 provides additional flexibility for system designers to appropriately set the device in desired mode as provided in Table 7-3. PD0 and PD1 pins impact channel groups 0-3 and 4-7 respectively. If all eight channels of DS320PR822 is used for a same PCI express link, then the PD1 and PD0 pins can be shorted and driven together. For most applications the RX_DET pin can be left floating for default settings. In SMBus/I2C mode each channel can be configured independently.
| PD0 | PD1 | RX_DET | Channels 0-3 Rx Common-mode Impedance | Channels 4-7 Rx Common-mode Impedance | COMMENTS |
|---|---|---|---|---|---|
| L | L | L0 | Always 50 Ω | Always 50 Ω | PCI Express Rx detection state machine is disabled. Recommended for non PCIe interface use case where the DS320PR822 is used as buffer with equalization. |
| L | L | L1 | Pre Detect: Hi-Z Post Detect: 50 Ω. | Pre Detect: Hi-Z Post Detect: 50 Ω. | Outputs polls until 3 consecutive valid detections |
| L | L | L2 | Pre Detect: Hi-Z Post Detect: 50 Ω. | Pre Detect: Hi-Z Post Detect: 50 Ω. | Outputs polls until 2 consecutive valid detections |
| L | L | L3 | NA | NA | Reserved |
| L | L | L4 (Float) | Pre Detect: Hi-Z Post Detect: 50 Ω. | Pre Detect: Hi-Z Post Detect: 50 Ω. | Tx polls every ?150 μs until valid termination is detected. Rx CM impedance held at Hi-Z until detection Reset by asserting PD0/1 high for 200 μs then low. |
| H | L | X | Hi-Z | Pre Detect: Hi-Z Post Detect: 50 Ω. | Reset Channels 0-3 signal path and set their Rx impedance to Hi-Z |
| L | H | X | Pre Detect: Hi-Z Post Detect: 50 Ω. | Hi-Z | Reset Channels 4-7 signal path and set their Rx impedance to Hi-Z. |
| H | H | X | Hi-Z | Hi-Z |
In PCIe applications PD0/1 pins can be connected to PCIe sideband signals PERST# with inverted polarity or one or more appropriate PRSNTx# signals to achieve desired RX detect functionality.