ZHCSKG3B September 2016 – February 2024 DS280DF810
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
The calibration clock is not part of the CDR’s PLL and thus is not used for clock and data recovery. The calibration clock is connected only to the PPM counter for each CDR. The PPM counter constrains the allowable lock ranges of the CDR according to the programmed values in the rate table or the manually entered data rates. The host should provide an input calibration clock signal of 25MHz frequency. Because this clock is not used for clock and data recovery, there are no stringent jitter requirements placed on this 25MHz calibration clock.