ZHCSDP9D October 2011 – April 2015 DS110DF410
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 典型應(yīng)用圖
- 5 修訂歷史記錄
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5
Programming
- 8.5.1 SMBus Strap Observation
- 8.5.2 Device Revision and Device ID
- 8.5.3 Control/Shared Register Reset
- 8.5.4 Interrupt Channel Flag Bits
- 8.5.5 SMBus Master Mode Control Bits
- 8.5.6 Resetting Individual Channels of the Retimer
- 8.5.7 Interrupt Status
- 8.5.8 Overriding the CTLE Boost Setting
- 8.5.9 Overriding the VCO Search Values
- 8.5.10 Overriding the Output Multiplexer
- 8.5.11 Overriding the VCO Divider Selection
- 8.5.12 Using the PRBS Generator
- 8.5.13 Using the Internal Eye Opening Monitor
- 8.5.14 Overriding the DFE Tap Weights and Polarities
- 8.5.15 Enabling Slow Rise/Fall Time on the Output Driver
- 8.5.16 Inverting the Output Polarity
- 8.5.17 Overriding the Figure of Merit for Adaptation
- 8.5.18 Setting the Rate and Subrate for Lock Acquisition
- 8.5.19 Setting the Adaptation/Lock Mode
- 8.5.20 Initiating Adaptation
- 8.5.21 Setting the Reference Enable Mode
- 8.5.22 Overriding the CTLE Settings Used for CTLE Adaptation
- 8.5.23 Setting the Output Differential Voltage
- 8.5.24 Setting the Output De-Emphasis Setting
- 8.6 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RHS|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RHS|48
訂購信息
10 Power Supply Recommendations
Figure 9 depicts an example power connections diagram for the DS110DF410. The supply (VDD) and ground (GND) Pins should be connected to power planes routed on adjacent layers of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance. Second, careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.1μF bypass capacitor should be connected to each VDD Pin such that the capacitor is placed as close as possible to the DS110DF410. Smaller body size capacitors can help facilitate proper component placement. Additionally, capacitor with capacitance in the range of 1 µF to 10 µF should be incorporated in the power supply bypassing design as well. These capacitors can be either tantalum or an ultra-low ESR ceramic.
Figure 9. Example Power Connections Diagram for the DS110DF410