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SNLS472A January 2014 – June 2017 DS110DF1610

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

ABB|196
- MPBGAF3B

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

5 Specifications

5.1 Absolute Maximum Ratings (DS110DF1610)

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
Supply voltage (VDD)		–0.5	2.75	V
LVCMOS input/output voltage		–0.5	2.75	V
Open-drain I/O supply voltage		–0.5	4	V
CML input voltage		–0.5	VDD + 0.5	V
CML input current		–30	30	mA
Storage temperature, T_stg		–40	150	°C
ESD Ratings	Human Body Model (HBM) - JESD22-A114F		>4	kV
ESD Ratings	Charged Device Model (CDM) - JESD22-A114F		>1	kV

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications

5.2 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

	MIN	TYP	MAX	UNIT
Supply voltage	2.375	2.5	2.625	V
Ambient temperature	–10	25	85	°C
SMBus (SDA, SCL), INTERR_IO		2.5	3.6	V

5.3 Thermal Characteristics

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

BOARD	θ JA (°C / W)	Ψ JT (°C / W)	Ψ JB (°C / W)
JEDEC	18.2	0.7	5.4
8x6 inches 10 layer	7.2	0.3	3.2
8x6 inches 20 layer	6.4	0.3	3.2
8x6 inches 30 layer	6.3	0.3	3.2

(1) For soldering specifications: See product folder at www.ti.com

5.4 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
R_baud	Input Data Rate	Full Rate	8.5		11.3	Gbps
		Half Rate	4.25		5.65
		Quarter Rate	2.125		2.825
		Eighth Rate	1.0625		1.4125
POWER SUPPLY
W	Power Consumption per Active Channel	CTLE only, 800mVp-p VOD, per channel, CDR locked		210		mW
		CDR Locking with CTLE only, 800mVp-p VOD, per channel		342.8
		CTLE and DFE, 800mVp-p VOD, per channel, CDR locked		235
		CDR Locking with CTLE and DFE, 800mVp-p VOD		367.8
		PRBS Checker		57
		PRBS Generator		83
W_STATIC	Static Power consumption	Power applied, no signals present		300		mW
LVCMOS
V _IH	High level input voltage		1.75		VDD	V
V_IL	Low level input voltage		GND		0.7	V
V_OH	High level output voltage	IOH = 4mA	2			V
V_OL	Low level output voltage	IOL = –4mA			0.4	V
I_IH	Input High Leakage current	Vinput = VDD, Open Drain pins			+30	mA
		Vinput = VDD, JTAG pins, Ref_CLK pins			+25
		Vinput = VDD, CLK_MON pin			+50
		Vinput = VDD, GPIO pins, EN_SMB pin			+75
I_IL	Input Low Leakage current	Vinput = 0V, Open Drain pins	–15			mA
		Vinput = 0V, JTAG pins, Ref_CLK pins	–45
		Vinput = 0V, CLK_MON pin	–50
		Vinput = 0V, GPIO pins, EN_SMB pin	–120
RX INPUTS
R_RD	DC Input Resistance		80	100	120	Ω
V_RX-IN	Input Differential Voltage				1600	mV_PP
V_cm-RX	Input common mode	Internal coupling cap	V_RX-IN / 4		VDD – (V_RX-IN/ 4)	V
TX OUTPUTS
V_OD	Output Differential Voltage	drv_sel_vod[5:0] = 31, DEM, C0 = default	825	1000	1200	mV_PP
V_OD	Output Differential Voltage	drv_sel_vod[5:0] = 15, DEM, C0 = default	400	525	675	mV_PP
ΔV_OD	Step Size for drv_sel_vod Control	Default DEM, and FIR settings		32		mV_PP
ΔV_ODVT	Change in Output Differentential Voltage due to Change in Temperature and Voltage			<15		mV_PP
R_Rd	Output Differential Resistance			100		Ω
R_RDZ	Output Resistance of Shutdown Termination Resistor	Resistor connects output pin to VDD		50		Ω
t_r, t_f	Output Rise/Fall Time	20% - 80% using 8T Pattern, fir_sel_edge = default		35		ps
I_OS	Output Short Circuit Current	Differential Driver Output pin short to GND drv_sel_vod = >4		–16		mA
RETIMER JITTER SPECS
J_TJ	Total Output Jitter	PRBS-7 pattern, measured to 1e-12 10.3125 Gbps data rate		8.6 (89)		ps (mUI)
J_TJ	Total Output Jitter	PRBS-7 pattern, measured to 1e-12 8.625 Gbps data rate		9.35 (80.6)		ps (mUI)
J_RJ	Output Random Jitter	PRBS-7 pattern, measured to 1e-12 10.3125 Gbps data rate		400 (4.125)		fs-rms (mUI-rms)
J_RJ	Output Random Jitter	PRBS-7 pattern, measured to 1e-12 8.625 Gbps data rate		439 (3.78)		fs-rms (mUI-rms)
J_DJ	Output Deterministic Jitter	PRBS-7 10.3125 Gbps data rate		3.15 (33)		ps (mUI)
J_DJ	Output Deterministic Jitter	PRBS-7 8.625 Gbps data rate		3.35 (28.9)		ps (mUI)
J_TRANS	Jitter Transfer			–6		dB
J_PEAK	Jitter Peaking			<0.1		dB
BW_PLL	PLL Bandwidth	Data Rate = 8.625 Gbps		6.35		MHz
BW_PLL	PLL Bandwidth	Data Rate = 11.3 Gbps		8.43		MHz
RETIMER TIMING SPECS
t_D	Propagation Delay from Rx inputs to Tx outputs	Data Rate = 10.3125Gbps, No Cross Point		480		ps
t_D	Propagation Delay from Rx inputs to Tx outputs	Data Rate = 10.3125 Gbps, Cross Point enabled		505		ps
t_SK	Channel To Channel Skew			<80		ps
RECOMMENDED REFERENCE CLOCK SPECS
REF_f	Input Reference Clock Frequency			25		MHz
				125
				312.5
REF_PPM	Reference Clock PPM Tolerance		–100		100	PPM
REF_TH	Reference Clock Input High Threshold	Differential mode	100			mV
REF_TL	Reference Clock Input Low Threshold	Differential mode			–100	mV
SMBus ELECTRICAL CHARACTERISTICS
V_IH	Input High Level Voltage	SDA and SCL	1.75		V_DDIO	V
V_IL	Input Low Level Voltage	SDA and SCL	GND		0.7	V
C_IN	Input Pin Capacitance			<5		pF
V_OL	Low Level Output Voltage	SDA and SCL VDDIO = 2.5V IOL = 2mA			0.4	V
RECOMMENDED SMBus SWITCHING CHARACTERISTICS
f_SCL	SCL Clock Frequency		10	100	400	kHz
t_HD:DAT	Data Hold Time		15			ns
t_SU:DAT	Data Setup Time		170			ns
RECOMMENDED JTAG SWITCHING CHARACTERISTICS
t_TCK	TCK Clock Period			100		ns
t_SU	TDI, TMI Setup Time to TCK			50		ns
t_HD	TDI, TMS Hold Time to TCK			50		ns
t_DLY	TCK Falling Edge to TDO			50		ns