ZHCSJB5B September 2019 – December 2019 DRV8904-Q1 , DRV8906-Q1 , DRV8908-Q1 , DRV8910-Q1 , DRV8912-Q1
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
The DRV89XX-Q1 is protected against various faults as summarized in Table 12.
| FAULT | CONDITION | CONFIGURATION | REPORT | HALF-BRIDGE | LOGIC | RECOVERY |
|---|---|---|---|---|---|---|
| VM Undervoltage (UVLO) | VVM < VUVLO
(Max. 4.5-V) |
— | nFAULT Pin
IC_STAT Register |
Hi-Z | Active | Automatic:
VVM > VUVLO |
| VDD Undervoltage (UVLO) | VVDD < VPOR
(Max 3-V) |
— | IC_STAT Register | Hi-Z | Reset | Automatic:
VVDD > VPOR |
| VM Overvoltage (OVP) | VVM > VOVP
(Min. 20-V) |
EXT_OVP = 0 | nFAULT Pin
IC_STAT Register |
Hi-Z | Active | Automatic:
VVM < VOVP |
| VVM > VOVP
(Min. 32-V) |
EXT_OVP = 1 | |||||
| Over Current Protection (OCP) | IOUT > IOCP
(Min. 1.3-A) |
OCP_REP = 0 | IC_STAT Register | Hi-Z | Active | CLR_FLT = 1 &
IOUT < IOCP |
| OCP_REP = 1 | nFAULT Pin
IC_STAT Register |
Hi-Z | Active | |||
| Open-Load Detect (OLD) | IOUT < IOLD
(Max. 15-mA) |
OLD_OP = 0
OLD_REP = 0 |
nFAULT Pin
IC_STAT Register |
Hi-Z | Active | CLR_FLT = 1 &
IMOTOR > IOLD |
| OLD_OP = 0
OLD_REP = 1 |
IC_STAT Register | Hi-Z | Active | |||
| OLD_OP = 1
OLD_REP = 0 |
nFAULT Pin
IC_STAT Register |
Operating | Active | |||
| OLD_OP = 1
OLD_REP = 1 |
IC_STAT Register | Operating | Active | |||
| RLOAD > ROLD
(Max. 100-kΩ) |
OLD_REP = 0 | nFAULT Pin
IC_STAT Register |
N/A | Active | CLR_FLT = 1 &
OLD Sequenced & RLOAD < ROLD |
|
| OLD_REP = 1 | IC_STAT Register | N/A | Active | |||
| Over-Temperature Warning (OTW) | TJ > TOTW
(Min. 120°C) |
OTW_REP = 0 | IC_STAT Register | Operating | Active | No Action |
| OTW_REP = 1 | nFAULT Pin
IC_STAT Register |
Operating | Active | Automatic:
TJ < TOTW –TOTW_HYS |
||
| Over-Temperature Shutdown (OTSD) | TJ > TOTSD
(Min. 150°C) |
— | nFAULT Pin
IC_STAT Register |
Hi-Z | Active | Automatic:
TJ < TOTSD –TOTSD_HYS |