ZHCSJB5B September 2019 – December 2019 DRV8904-Q1 , DRV8906-Q1 , DRV8908-Q1 , DRV8910-Q1 , DRV8912-Q1
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
The synchronous rectification of the half bridges operating in PWM mode (OUT4, OUT5 and OUT6) are enabled by setting the corresponding HBX_FW bits in free-wheeling control register (FW_CTRL_1 and FW_CTRL_2). By default, the synchronous rectification mode is disabled.
Figure 38 shows the parallel operation of half-bridges in PWM mode with synchronous rectification disabled. As shown in this figure, during the PWM off time, the high-side diode of the OUT4, OUT5 and OUT6 conducts to close the current path required for motor.
When synchronous rectification mode is enabled, the high-side FETs of OUT4, OUT5 and OUT6 starts conducting during the PWM OFF time to close the motor current path as shown in Figure 39.
Figure 38. Parallel Mode (PWM with Synchronous Rectification = OFF)
Figure 39. Parallel Mode (PWM with Synchronous Rectification = ON)