ZHCSER7C October 2015 – November 2018 DRV8885
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER SUPPLIES (VM, DVDD, AVDD) | ||||||
| VVM | VM operating voltage | 8 | 37 | V | ||
| IVM | VM operating supply current | VM ≈ 8 to 35 V, ENABLE = 1, nSLEEP = 1, No motor load | 5 | 8 | mA | |
| IVMQ | VM sleep mode supply current | nSLEEP = 0; TA = 25°C | 20 | μA | ||
| nSLEEP = 0; TA = 125°C (1) | 40 | |||||
| tSLEEP | Sleep time | nSLEEP = 0 to sleep-mode | 50 | 200 | μs | |
| tWAKE | Wake-up time | nSLEEP = 1 to output transition | 0.85 | 1.5 | ms | |
| tON | Turn-on time | VM > UVLO to output transition | 0.85 | 1.5 | ms | |
| VDVDD | Internal regulator voltage | 0- to 1-mA external load | 2.9 | 3.3 | 3.6 | V |
| VAVDD | Internal regulator voltage | No external load | 4.5 | 5.0 | 5.5 | V |
| CHARGE PUMP (VCP, CPH, CPL) | ||||||
| VVCP | VCP operating voltage | VM > 8 V | VM + 5.5 | V | ||
| LOGIC-LEVEL INPUTS (STEP, DIR, ENABLE, nSLEEP, M1) | ||||||
| VIL | Input logic low voltage | 0 | 0.8 | V | ||
| VIH | Input logic high voltage | 1.6 | 5.3 | V | ||
| VHYS | Input logic hysteresis | 100 | mV | |||
| IIL | Input logic low current | VIN = 0 V | –1 | 1 | μA | |
| IIH | Input logic high current | VIN = 5.0 V | 100 | μA | ||
| RPD | Pulldown resistance | To GND | 100 | kΩ | ||
| tPD | Propagation delay | STEP to current change | 1.2 | μs | ||
| TRI-LEVEL INPUT (M0, TRQ) | ||||||
| VIL | Tri-level input logic low voltage | 0 | 0.65 | V | ||
| VIZ | Tri-level input Hi-Z voltage | 1.1 | V | |||
| VIH | Tri-level input logic high voltage | 1.5 | 5.3 | V | ||
| IIL | Tri-level input logic low current | VIN = 0 V | –80 | μA | ||
| IIZ | Tri-level input Hi-Z current | VIN = 1.3 V | –5 | 5 | μA | |
| IIH | Tri-level input logic high current | VIN = 5.0 V | 155 | μA | ||
| RPD | Tri-level pulldown resistance | To GND | 18 | 32 | 50 | kΩ |
| RPU | Tri-level pullup resistance | To DVDD | 30 | 60 | 90 | kΩ |
| QUAD-LEVEL INPUT (DECAY) | ||||||
| VI1 | Quad-level input voltage 1 | 5% resistor 5 kΩ to GND | 0.07 | 0.11 | 0.13 | V |
| VI2 | Quad-level input voltage 2 | 5% resistor 15 kΩ to GND | 0.24 | 0.32 | 0.40 | V |
| VI3 | Quad-level input voltage 3 | 5% resistor 45 kΩ to GND | 0.71 | 0.97 | 1.20 | V |
| VI4 | Quad-level input voltage 4 | 5% resistor 135 kΩ to GND | 2.12 | 2.90 | 3.76 | V |
| IO | Output current | To GND | 14 | 22 | 30 | μA |
| CONTROL OUTPUTS (nFAULT) | ||||||
| VOL | Output logic low voltage | IO = 1 mA, RPULLUP = 4.7 kΩ | 0.5 | V | ||
| IOH | Output logic high leakage | VO = 5.0 V, RPULLUP = 4.7 kΩ | –1 | +1 | μA | |
| MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2) | ||||||
| RDS(ON) | High-side FET on resistance | VM = 24 V, I = 1 A, TA = 25°C | 440 | 490 | mΩ | |
| RDS(ON) | Low-side FET on resistance | VM = 24 V, I = 1 A, TA = 25°C | 420 | 460 | mΩ | |
| tRISE(2) | Output rise time | 100 | ns | |||
| tFALL(2) | Output fall time | 100 | ns | |||
| tDEAD(2) | Output dead time | 200 | ns | |||
| Vd(2) | Body diode forward voltage | IOUT = 0.5 A | 0.7 | 1.0 | V | |
| PWM CURRENT CONTROL (RREF) | ||||||
| ARREF | RREF transimpedance gain | 28.1 | 30 | 31.9 | kAΩ | |
| VRREF | RREF voltage | RREF = 18 to 132 kΩ | 1.18 | 1.232 | 1.28 | V |
| tOFF | PWM off-time | 20 | μs | |||
| CRREF | Equivalent capacitance on RREF | 10 | pF | |||
| tBLANK | PWM blanking time | IRREF = 1.5 A, 63% to 100% current setting | 1.5 | µs | ||
| IRREF = 1.5 A, 0% to 63% current setting | 1.0 | |||||
| ΔITRIP | Current trip accuracy | IRREF = 1.0 A, 10% to 20% current setting, 1% reference resistor | –25% | 25% | ||
| IRREF = 1.0 A, 20% to 63% current setting, 1% reference resistor | –12.5% | 12.5% | ||||
| IRREF = 1.0 A, 71% to 100% current setting, 1% reference resistor | –6.25% | 6.25% | ||||
| PROTECTION CIRCUITS | ||||||
| VUVLO | VM UVLO | VM falling; UVLO report | 7.8 | V | ||
| VM rising; UVLO recovery | 8.0 | |||||
| VUVLO,HYS | Undervoltage hysteresis | Rising to falling threshold | 100 | mV | ||
| VCPUV | Charge pump undervoltage | VCP falling; CPUV report | VM + 2.0 | V | ||
| IOCP | Overcurrent protection trip level | Current through any FET | 2.3 | A | ||
| tOCP | Overcurrent deglitch time | 1.3 | 1.9 | 2.8 | μs | |
| tRETRY | Overcurrent retry time | 1 | 1.6 | ms | ||
| TTSD(2) | Thermal shutdown temperature | Die temperature TJ | 150 | °C | ||
| THYS(2) | Thermal shutdown hysteresis | Die temperature TJ | 20 | °C | ||