SLVSET1 August 2018 DRV8873
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- PWP|24
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- PWP|24
訂購信息
7.3.1.1 Control Modes
The device output consists of four N-channel MOSFETs that are designed to drive high current. The MOSFETs are controlled by two logic inputs, EN/IN1 and PH/IN2, in three different input modes to support various commutation and control methods, as shown in the logic tables (Table 4, Table 5, and Table 6). In the Independent PWM mode, the fault handling is performed independently for each half bridge. For example, if an overcurrent condition (OCP) is detected in half-bridge 1, only the half-bridge 1 output (OUT1) is disabled and half-bridge 2 continues to operate based on the IN2 input.
Table 4. PH/EN Mode Truth Table
| nSLEEP | DISABLE | EN/IN1 | PH/IN2 | OUT1 | OUT2 |
|---|---|---|---|---|---|
| 0 | X | X | X | Hi-Z | Hi-Z |
| 1 | 1 | X | X | Hi-Z | Hi-Z |
| 1 | 0 | 0 | X | H | H |
| 1 | 0 | 1 | 0 | L | H |
| 1 | 0 | 1 | 1 | H | L |
Table 5. PWM Mode Truth Table
| nSLEEP | DISABLE | EN/IN1 | PH/IN2 | OUT1 | OUT2 |
|---|---|---|---|---|---|
| 0 | X | X | X | Hi-Z | Hi-Z |
| 1 | 1 | X | X | Hi-Z | Hi-Z |
| 1 | 0 | 0 | 0 | Hi-Z | Hi-Z |
| 1 | 0 | 0 | 1 | L | H |
| 1 | 0 | 1 | 0 | H | L |
| 1 | 0 | 1 | 1 | H | H |
Table 6. Independent Mode Truth Table
| nSLEEP | DISABLE | EN/IN1 | PH/IN2 | OUT1 | OUT2 |
|---|---|---|---|---|---|
| 0 | X | X | X | Hi-Z | Hi-Z |
| 1 | 1 | X | X | Hi-Z | Hi-Z |
| 1 | 0 | 0 | 0 | L | L |
| 1 | 0 | 0 | 1 | L | H |
| 1 | 0 | 1 | 0 | H | L |
| 1 | 0 | 1 | 1 | H | H |
The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. When using PWM mode (MODE = 1), switching between driving and braking typically is best. For example, to drive a motor forward with 50% of its maximum revolutions per minute (RPM), the IN1 pin is high and the IN2 pin is low during the driving period. During the other period in this example, the IN1 pin is high and the IN2 pin is high.
Figure 10. Half-Bridge Current Paths In the Independent PWM mode, to independently put the outputs of the half bridge in the high-impedance (Hi-Z) state, the OUT1_DIS or OUT2_DIS bit in the IC3 register must be set to 1b. Writing a logic 1 to the OUT1_DIS bit disables the OUT1 output. Writing a logic 1 to the OUT2_DIS bit disables the OUT2 output. The default value in these registers is 0b. The option to independently set the outputs of the half bridge in the Hi-Z state is not available for the hardware version of the device.