SLVSB19D February 2012 – March 2015 DRV8834
PRODUCTION DATA.

| PIN | I/O | DESCRIPTION | EXTERNAL COMPONENTS OR CONNECTIONS |
||
|---|---|---|---|---|---|
| NAME | HTSSOP | VQFN | |||
| POWER AND GROUND | |||||
| GND | 21, PPAD |
18, PPAD |
— | Device ground | Both the GND pin and device PowerPAD must be connected to ground |
| VM | 18, 19 | 15, 16 | — | Bridge A power supply | Connect to motor supply. A 10-µF (minimum) capacitor to GND is recommended. |
| VINT | 20 | 17 | — | Internal supply | Bypass to GND with 2.2-μF (minimum), 6.3-V capacitor. Can be used to provide logic high voltage for configuration pins (except nSLEEP). |
| VREFO | 24 | 21 | O | Reference voltage output | May be connected to AVREF/BVREF inputs. Do not place a bypass capacitor on this pin. |
| VCP | 17 | 14 | O | High-side gate drive voltage | Connect a 0.01-μF, 16-V (minimum) X7R ceramic capacitor to VM. |
| CONTROL (INDEXER MODE OR PHASE/ENABLE MODE) | |||||
| nENBL/AENBL | 10 | 7 | I | Step motor enable/Bridge A enable | Indexer mode: Logic low enables all outputs. Phase/enable mode: Logic high enables the AOUTx outputs. Internal pulldown. |
| STEP/BENBL | 11 | 8 | I | Step input/Bridge B enable | Indexer mode: Rising edge moves indexer to next step. Phase/enable mode: Logic high enables the BOUTx outputs. Internal pulldown. |
| DIR/BPHASE | 12 | 9 | I | Direction input/Bridge B Phase | Indexer mode: Level sets direction of step. Phase/enable mode: Logic high sets BOUT1 high, BOUT2 low. Internal pulldown. |
| M0/APHASE | 13 | 10 | I | Microstep mode/Bridge A phase | Indexer mode: Controls microstep mode (full, half, up to 1/32-step) along with M1. Phase/enable mode: Logic high sets AOUT1 high, AOUT2 low. Internal pulldown. |
| M1 | 14 | 11 | I | Microstep mode/Disable state | Indexer mode: Controls microstep mode (full, half, up to 1/32-step) along with M0. Phase/enable mode: Determines the state of the outputs when xENBL = 0. Internal pulldown. |
| CONFIG | 15 | 12 | I | Device configuration | Logic high to put the device in indexer mode. Logic low to put the device into phase/enable mode. State is latched at power up and sleep exit. Internal pulldown. |
| nSLEEP | 1 | 22 | I | Sleep mode input | Logic high to enable device, logic low to enter low-power sleep mode and reset all internal logic. |
| AVREF | 22 | 19 | I | Bridge A current set reference input | Reference voltage for AOUT winding current. In Indexer Mode, it should be tied to a reference voltage for the internal DAC (for example, VREFO). In Phase/Enable Mode, an external DAC can drive it for microstepping. |
| BVREF | 23 | 20 | I | Bridge B current set reference input | Reference voltage for BOUT winding current. In Indexer Mode, it should be tied to a reference voltage for the internal DAC (for example, VREFO). In Phase/Enable Mode, an external DAC can drive it for microstepping. |
| ADECAY | 3 | 24 | I | Decay mode for bridge A | Determines decay mode for H-Bridge A (or A and B in indexer mode) – slow, fast or mixed decay |
| BDECAY | 2 | 23 | I | Decay mode for bridge B | Determines decay mode for H-Bridge B – slow, fast or mixed decay |
| STATUS | |||||
| nFAULT | 16 | 13 | OD | Fault output | Logic low when in fault condition (overtemp, overcurrent, undervoltage) |
| OUTPUT | |||||
| AISEN | 5 | 2 | IO | Bridge A ground/Isense | Connect to current sense resistor for bridge A, or GND if current control not needed |
| BISEN | 8 | 5 | IO | Bridge B ground/Isense | Connect to current sense resistor for bridge B, or GND if current control not needed |
| AOUT1 | 4 | 1 | O | Bridge A output 1 | Connect to motor winding A |
| AOUT2 | 6 | 3 | O | Bridge A output 2 | |
| BOUT1 | 9 | 6 | O | Bridge B output 1 | Connect to motor winding B |
| BOUT2 | 7 | 4 | O | Bridge B output 2 | |