SLVSA11G October 2009 – November 2015 DRV8828
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- PWP|28
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- PWP|28
訂購信息
5 Pin Configuration and Functions
PWP Package
28-Pin HTSSOP With Thermal Pad
Top View
Pin Functions
| PIN | I/O(1) | DESCRIPTION | EXTERNAL COMPONENTS OR CONNECTIONS |
|
|---|---|---|---|---|
| NAME | NO. | |||
| POWER AND GROUND | ||||
| GND | 14, 28 | - | Device ground | |
| VM | 4, 11 | - | Bridge power supply | Connect to motor supply (8 - 45 V). Both pins must be connected to same supply. |
| V3P3OUT | 15 | O | 3.3-V regulator output | Bypass to GND with a 0.47-μF 6.3-V ceramic capacitor. Can be used to supply VREF. |
| CP1 | 1 | I/O | Charge pump flying capacitor | Connect a 0.01-μF 50-V capacitor between CP1 and CP2. |
| CP2 | 2 | I/O | Charge pump flying capacitor | |
| VCP | 3 | I/O | High-side gate drive voltage | Connect a 0.1-μF 16-V ceramic capacitor and a 1-MΩ resistor to VM. |
| CONTROL | ||||
| ENBL | 21 | I | Bridge enable | Logic high to enable H-bridge. Internal pulldown. |
| PHASE | 20 | I | Bridge phase (direction) | Logic high sets OUT1 high, OUT2 low. Internal pulldown. |
| I0 | 23 | I | Current set inputs | Sets winding current as a percentage of full-scale. Internal pulldown. |
| I1 | 24 | I | ||
| I2 | 25 | I | ||
| I3 | 26 | I | ||
| I4 | 27 | I | ||
| DECAY | 19 | I | Decay mode | Low = slow decay, open = mixed decay, high = fast decay Internal pulldown and pullup. |
| nRESET | 16 | I | Reset input | Active-low reset input initializes internal logic and disables the H-bridge outputs. Internal pulldown. |
| VREF | 12, 13 | I | Current set reference input | Reference voltage for winding current set. Both pins must be connected together on the PCB. A 0.01-µF bypass capacitor to GND is recommended. |
| nSLEEP | 17 | I | Sleep mode input | Logic high to enable device, logic low to enter low-power sleep mode. Internal pulldown. |
| NC | 22 | No connect | Leave this pin unconnected. | |
| STATUS | ||||
| nFAULT | 18 | O/D | Fault | Logic low when in fault condition (overtemp, overcurrent) |
| OUTPUT | ||||
| ISEN | 6, 9 | I/O | Bridge ground / Isense | Connect to current sense resistor. Both pins must be connected together on the PCB. |
| OUT1 | 5, 10 | O | Bridge output 1 | Connect to motor winding. Both pins must be connected together on the PCB. |
| OUT2 | 7, 8 | O | Bridge output 2 | |
(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output