ZHCSG57B March 2017 – December 2018 DRV8702D-Q1 , DRV8703D-Q1
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The MODE pin of the device determines the control interface and latches on power-up or when exiting sleep mode. Figure 32 shows an overview of the internal circuit of the MODE pin.
Figure 32. MODE Pin Block Diagram Table 5 lists the different control interfaces that can be set via MODE pin at power-up or when exiting sleep mode.
| MODE | CONTROL INTERFACE |
|---|---|
| 1 | PWM control interface without current regulation |
| Hi-Z | PWM control interface with current regulation |
During the device power-up sequence, the DVDD pin is enabled first. Then the MODE pin latches. Finally the AVDD pin is enabled. For setting PWM control interface, TI does not recommended connecting the MODE pin to the AVDD pin. Instead the MODE pin should be connected to an external 5-V or 3.3-V supply or to the DVDD pin if not driven by an external microcontroller (MCU).