ZHCSG57B March 2017 – December 2018 DRV8702D-Q1 , DRV8703D-Q1
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Table 3, and Table 4 are the device logic tables. An X denotes a don’t care input or output.
NOTE
Any other input logic combinations, aside from the ones mentioned in Table 3 and Table 4, result in an error, and the device will trigger a fault.
| nSLEEP | IN1 | IN2 | GH | GL | SH | AVDD/DVDD | Description |
|---|---|---|---|---|---|---|---|
| 0 | X | X | X | X | Hi-Z | Disabled | Sleep mode ½-bridge disabled |
| 1 | 0 | 0 | 0 | 1 | L | Enabled | ½-bridge low side on |
| 1 | 1 | 0 | 1 | 0 | H | Enabled | ½-bridge high side on |
| nSLEEP | IN1 | IN2 | GH | GL | SH | AVDD/DVDD | Description |
|---|---|---|---|---|---|---|---|
| 0 | X | X | X | X | Hi-Z | Disabled | Sleep mode ½-bridge disabled |
| 1 | 0 | 0 | 0 | 0 | Hi-Z | Enabled | ½-bridge is in tri-state |
| 1 | 1 | 0 | 1 | 0 | H | Enabled | ½-bridge high-side on |
| 1 | 1 | 1 | 0 | 1 | L | Enabled | ½-bridge low-side on |
If MODE = Hi-Z is selected, the device performs current regulation (refer to the Current Regulation section). Having both the input (INx) pins high puts the motor in brake mode (low-side slow decay). If MODE = 1 is selected, current regulation is disabled and must be performed externally using a MCU. With MODE = 1, the load current recirculation occurs through the high-side FET as shown in Figure 31.