7.3.1 Bridge Control

The DRV8701E is controlled using a PH/EN interface. The following logic table (Table 1) gives the full H-bridge state when driving a single brushed DC motor. Note that Table 1 does not take into account the current control built into the DRV8701E. Positive current is defined in the direction of xOUT1 → xOUT2.

The DRV8701P is controlled using a PWM interface (IN1/IN2). The following logic table (Table 2) gives the full H-bridge state when driving a single brushed DC motor. Note that Table 2 does not take into account the current control built into the DRV8701P. Positive current is defined in the direction of xOUT1 → xOUT2.

Figure 19. H-Bridge Operational States

7.3.2 Half-Bridge Operation

The DRV8701 can be used to drive only a single half-bridge instead of a full H-bridge. To operate in this mode, leave GH1 and GL1 disconnected. Also, connect a 1/10 W, 330-Ω 5% resistor from SH1 to GND.

Figure 20. Half-H Bridge Operation Mode

For the DRV8701E, this mode is controlled by tying the PH pin low. Table 3 gives the control scheme. EN = 1 enables the high-side FET, and EN = 0 enables the low-side FET. EN = 1 and PH = 1 is an invalid state.

For the DRV8701P, Table 4 gives the control scheme. IN1 = 1 and IN2 = 0 is an invalid state.

7.3.3 Current Regulation

The maximum current through the motor winding is regulated by a fixed off-time PWM current regulation, or current chopping. When an H-bridge is enabled in forward or reverse drive, current rises through the winding at a rate dependent on the DC voltage and inductance of the winding. After the current hits the current chopping threshold, the bridge enters a brake (low-side slow decay) mode until t_OFF has expired.

Note that immediately after the current is enabled, the voltage on the SP pin is ignored for a period of time (t_BLANK) before enabling the current sense circuitry.

The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the SP pin, multiplied by a factor of A_V, with a reference voltage from the VREF pin. The factor A_V is the shunt amplifier gain, which is 20 V/V in the DRV8701.

The chopping current is calculated as follows:

Equation 1.

Example: If a 50 mΩ sense resistor is used and VREF = 3.3 V, the full-scale chopping current will be 3.25 A. A_V is 20 V/V and V_OFF is assumed to be 50 mV in this example.

For DC motors, current regulation is generally used to limit the start-up and stall current of the motor. If the current regulation feature is not needed, it can be disabled by tying VREF directly to AVDD and tying SP and SN to GND.

Figure 21. Sense Amplifier and Current Chopping Operation

During brake mode (slow decay), current is recirculated through the low-side FETs. Because current is not flowing through the sense resistor, SO does not represent the motor current.

7.3.4 Amplifier Output SO

The SO pin on the DRV8701 outputs an analog voltage equal to the voltage seen across the SP and SN pins multiplied by A_V. The factor A_V is the shunt amplifier gain, which is 20 V/V in the DRV8701. SO is only valid during forward or reverse drive. The H-bridge current is approximately equal to:

Equation 2.

When SP and SN are 0 V, SO outputs the amplifier offset voltage V_OFF. No capacitor is required on the SO pin.

Figure 22. Sense Amplifier Diagram

If the voltage across SP and SN exceeds 1 V, then the DRV8701 flags an overcurrent condition.

The SO pin can source up to 5 mA of current. If the pin is shorted to GND, or if a higher-current load is driven by this pin, the output acts as a constant-current source. The output voltage is not representative of the H-bridge current in this state.

This shunt amplifier feature can be disabled by tying the SP and SN pins to GND. When the amplifier is disabled, current regulation is also disabled.

Figure 23. Sense Amplifier Output

7.3.5 PWM Motor Gate Drivers

The DRV8701 contains gate drivers for a single H-bridge with external NMOS FETs. Figure 24 shows a block diagram of the gate driver circuitry.

Figure 24. PWM Motor Gate Drivers

Gate drivers inside the DRV8701 directly drive N-channel MOSFETs, which drive the motor current. The high-side gate drive is supplied by the charge pump, while the low-side gate drive voltage is generated by an internal regulator.

The peak drive current of the gate drivers is adjustable through the IDRIVE pin. Peak source currents may be set to 6, 12.5, 25, 100, or 150 mA. The peak sink current is approximately 2× the peak source current. Adjusting the peak current changes the output slew rate, which also depends on the FET input capacitance and gate charge.

The peak drive current is selected by setting the value of the R_IDRIVE resistor on the IDRIVE pin or by forcing a voltage onto the IDRIVE pin (see Table 6 for details).

Fast switching times can cause extra voltage noise on VM and GND. This can be especially due to a relatively slow reverse-recovery time of the low-side body diode, where it conducts reverse-bias momentarily, being similar to shoot-through. Slow switching times can cause excessive power dissipation since the external FETs take a longer time to turn on and turn off.

When changing the state of the output, the peak current (I_DRIVE) is applied for a short drive period (t_DRIVE) to charge the gate capacitance. After this time, a weaker current source (I_HOLD) is used to keep the gate at the desired state. When selecting the gate drive strength for a given external FET, the selected current must be high enough to fully charge and discharge the gate during t_DRIVE, or excessive power will be dissipated in the FET.

During high-side turn-on, the low-side gate is pulled low with a strong pull-down (I_STRONG). This prevents the low-side FET Q_GS from charging and keeps the FET off, even when there is fast switching at the outputs.

The pre-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and low-side FETs from conducting at the same time. When switching FETs on, this handshaking prevents the high- or low-side FET from turning on until the opposite FET has been turned off.

Figure 25. Gate Driver Output to Control External FETs

Q_GD Miller charge

When a FET gate is turned on, three different capacitances must be charged.

• Q_GS – Gate-to-source charge
• Q_GD – Gate-to-drain charge (miller charge)
• Remaining Q_G

The FET output is slewing primarily during the Q_GD charge.

Figure 26. Example FET Gate Charging Profile

7.3.6 IDRIVE Pin

The rise and fall times of the H-bridge output (SHx pins) can be adjusted by setting the IDRIVE resistor value or forcing a voltage onto the IDRIVE pin. The FET gate voltage ramps faster if a higher IDRIVE setting is chosen. The FET gate ramp directly affects the H-bridge output rise and fall time.

Tying IDRIVE to GND selects the lowest drive setting of 6-mA source and 12.5-mA sink. If this pin is left unconnected, then the 100-mA source and 200-mA sink setting are selected.

If IDRIVE is shorted to AVDD, then the VDS OCP monitor on the high-side FETs is disabled. In this setting, the gate driver is configured as 25-mA source and 50-mA sink.

Figure 27. IDRIVE Pin Internal Circuitry

Table 6. IDRIVE Pin Resistor Settings

<1 kΩ to GND	33 kΩ ±5% to GND 200 kΩ ±5% to GND	>500 kΩ to GND, High-Z	68 kΩ ±5% to AVDD	<1 kΩ to AVDD
IDRIVE	IDRIVE	IDRIVE	IDRIVE	IDRIVE
6 / 12.5 mA	12.5 / 25 mA (33 kΩ) 25 / 50 mA (200 kΩ)	100 / 200 mA	150 / 300 mA	25 / 50 mA HS OCP monitor off

7.3.7 Dead Time

Dead time (t_DEAD) is measured as the time when SHx is High-Z between turning off one of the H-bridge FETs and turning on the other. For example, the output is High-Z between turning off the high-side FET and turning on the low-side FET.

The DRV8701 inserts a digital dead time of approximately 150 ns. The total dead time also includes the FET gate turn-on time.

The total dead time is dependent on the IDRIVE resistor setting because a portion of the FET gate ramp (GHx and GLx pins) includes the observable dead time.

7.3.8 Propagation Delay

The propagation delay time (t_DELAY) is measured as the time between an input edge to an output change. This time is composed of two parts: an input deglitch time and output slewing delay. The input deglitcher prevents noise on the input pins from affecting the output state.

The gate drive slew rate also contributes to the delay time. For the output to change state during normal operation, first, one FET must be turned off. The FET gate is ramped down according to the IDRIVE setting, and the observed propagation delay ends when the FET gate has fallen below the threshold voltage.

7.3.9 Overcurrent V_DS Monitor

The gate driver circuit monitors the V_DS voltage of each external FET when it is driving current. When the voltage monitored is greater than the OCP threshold voltage (V_{DS OCP}), after the OCP deglitch time (t_OCP) has expired, an OCP condition will be detected.

Figure 28. Overcurrent VDS Monitors

When IDRIVE is shorted to AVDD, the V_DS OCP monitor on the high-side FETs is disabled. In cases where the VM supplied to the DRV8701 can be different from the external H-bridge supply, this setting must be used in order to prevent false overcurrent detection. In this mode, the IDRIVE current is set to 25-mA source and 50-mA sink.

7.3.10 Charge Pump

A charge pump is integrated to supply a high-side NMOS gate drive voltage of V_HGS. The charge pump requires a capacitor between the VM and VCP pins. Additionally a low-ESR ceramic capacitor is required between pins CPH and CPL. When VM is below 12 V, this charge pump behaves as a doubler and generates VCP = 2 × VM – 1.5 V if unloaded. Above VM = 12 V, the charge pump regulates VCP such that VCP = VM + 9.5 V.

Figure 29. Charge Pump Diagram

7.3.11 LDO Voltage Regulators

Two LDO regulators are integrated into the DRV8701. They can be used to provide the supply voltage for a low-power microcontroller or other low-current devices. For proper operation, bypass the AVDD and DVDD pins to GND using ceramic capacitors.

The AVDD output voltage is nominally 4.8 V, and the DVDD output is nominally 3.3 V. When the AVDD or DVDD current load exceeds 30 mA, the LDO behaves like a constant current source. The output voltage drops significantly with currents greater than this limit.

Note that AVDD and DVDD are disabled when the device is in sleep mode (nSLEEP = 0). In addition, when an overtemperature (TSD) or undervoltage (UVLO) fault is encountered, the AVDD regulator is shut off.

Figure 30. AVDD and DVDD LDOs

The power dissipated in the DRV8701 due to these LDOs may be approximated by:

For example at VM = 24 V, drawing 10 mA out of both AVDD and DVDD results in a power dissipation of:

7.3.12 Gate Drive Clamp

A clamping structure limits the gate drive output voltage to V_{GS CLAMP} to protect the power FETs from damage. The positive voltage clamp is realized using a series of diodes. The negative voltage clamp uses the body diodes of the internal gate driver FET.

Figure 31. Gate Drive Clamp Diagram

7.3.13 Protection Circuits

The DRV8701 is fully protected against VM undervoltage, charge pump undervoltage, overcurrent, gate driver shorts, and overtemperature events.

7.3.14 Reverse Supply Protection

The following circuit may be implemented to protect the system from reverse supply conditions. This circuit requires the following additional components:

• NMOS FET
• npn BJT
• Diode
• 10-kΩ resistor
• 43-kΩ resistor

Figure 32. Reverse Supply Protection External Circuitry

Table 8. Functional Modes

7.4.1 Operating DRV8701 and H-Bridge on Separate Supplies

The DRV8701 can operate with a different supply voltage (VM) than the system H-bridge supply (VBAT). Case 1 describes normal operation when VM and VBAT are roughly the same. Special considerations must be taken into account for Cases 2, 3, and 4.

• Case 1: VM ≈ VBAT. Recommended operation
• Case 2: VM > VBAT. IDRIVE must be shorted to AVDD to disable the high-side OCP. The IDRIVE current is fixed at 25-mA source and 50-mA sink. This case can allow the driver to better enhance the external FETs for VBAT < 11.5 V, or operate down to a lower supply voltage below 5.9 V.
• Case 3: VM > VBAT (higher than Case 2). IDRIVE must be shorted to AVDD to disable the high-side OCP. This case can also allow the driver to better enhance the external FETs, or operate down to a lower supply voltage below 5.9 V. The IDRIVE current is fixed at 25-mA source and 50-mA sink. Excess gate drive current may be driven through the DRV8701 gate clamps causing additional power dissipation in the DRV8701.
• Case 4: VM < VBAT. The high-side FETs may not be in saturation. There may be a significant voltage drop across the high-side FET when driving current. This causes high power dissipation in the external FET. When operating in Case 4, the external FET threshold voltage must be greater than 2 V. Otherwise the DRV8701 will report a pre-driver fault whenever the FET is out of saturation.

Figure 33. VM Operating Range Based on Motor Supply Voltage

When nSLEEP is low, VM may be reduced down to 0 V with up to 45 V present at VBAT. However, nSLEEP should not be brought high until VM is supplied with a voltage aligning with one of the cases outlined above.