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ZHCSDO0A March 2015 – May 2015 DRV8701

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RGE|24
- MPQF124G

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range referenced with respect to GND (unless otherwise noted) ⁽¹⁾

	MIN	MAX	UNIT
Power supply voltage (VM)	–0.3	47	V
Power supply voltage ramp rate (VM)	0	2	V/µs
Charge pump voltage (VCP, CPH)	–0.3	VM + 12	V
Charge pump negative switching pin (CPL)	–0.3	VM	V
Internal logic regulator voltage (DVDD)	–0.3	3.8	V
Internal analog regulator voltage (AVDD)	–0.3	5.75	V
Control pin voltage (PH, EN, IN1, IN2, nSLEEP, nFAULT, VREF, IDRIVE, SNSOUT)	–0.3	5.75	V
High-side gate pin voltage (GH1, GH2)	–0.3	VM + 12	V
Continuous phase node pin voltage (SH1, SH2)	–1.2	VM + 1.2	V
Pulsed 10 µs phase node pin voltage (SH1, SH2)	–2.0	VM + 2	V
Low-side gate pin voltage (GL1, GL2)	–0.3	12	V
Continuous shunt amplifier input pin voltage (SP, SN)	–0.5	1	V
Pulsed 10-µs shunt amplifier input pin voltage (SP, SN)	–1	1	V
Shunt amplifier output pin voltage (SO)	–0.3	5.75	V
Open-drain output current (nFAULT, SNSOUT)	0	10	mA
Gate pin source current (GH1, GL1, GH2, GL2)	0	250	mA
Gate pin sink current (GH1, GL1, GH2, GL2)	0	500	mA
Shunt amplifier output pin current (SO)	0	5	mA
Operating junction temperature, T_J	–40	150	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM) ESD stress voltage⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM) ESD stress voltage⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
VM	Power supply voltage range	5.9	45	V
VCC	Logic level input voltage	0	5.5	V
VREF	Reference RMS voltage range (VREF)	0.3⁽¹⁾	AVDD	V
ƒ_PWM	Applied PWM signal (PH/EN or IN1/IN2)		100	kHz
I_AVDD	AVDD external load current		30⁽²⁾	mA
I_DVDD	DVDD external load current		30⁽²⁾	mA
I_SO	Shunt amplifier output current loading (SO)		5	mA
T_A	Operating ambient temperature	–40	125	°C

(1) Operational at VREF = 0 to 0.3 V, but accuracy is degraded

(2) Power dissipation and thermal limits must be observed

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DRV8701	UNIT
		RGE (VQFN)
		24 PINS
R_θJA	Junction-to-ambient thermal resistance	34.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	37.1	°C/W
R_θJB	Junction-to-board thermal resistance	12.2	°C/W
ψ_JT	Junction-to-top characterization parameter	0.6	°C/W
ψ_JB	Junction-to-board characterization parameter	12.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
POWER SUPPLIES (VM, AVDD, DVDD)
VM	VM operating voltage			5.9		45	V
I_VM	VM operating supply current	VM = 24 V; nSLEEP high			6	9.5	mA
I_VMQ	VM sleep mode supply current	nSLEEP = 0 VM = 24 V	T_A = 25°C		9	15	μA
I_VMQ	VM sleep mode supply current	nSLEEP = 0 VM = 24 V	T_A = 125°C⁽¹⁾		14	25	μA
t_SLEEP	Sleep time	nSLEEP low to sleep mode				100	μs
t_WAKE	Wake-up time	nSLEEP high to output change				1	ms
t_ON	Turn-on time	VM > UVLO to output transition				1	ms
DVDD	Internal logic regulator voltage	External load 0 to 30 mA		3.0	3.3	3.5	V
AVDD	Internal logic regulator voltage	External load 0 to 30 mA		4.4	4.8	5.2	V
CHARGE PUMP (VCP, CPH, CPL)
VCP	VCP operating voltage	VM = 12 V; I_VCP = 0 to 12 mA		20.5	21.5	22.5	V
		VM = 8 V; I_VCP = 0 to 10 mA		13.5	14.4	15
		VM = 5.9 V; I_VCP = 0 to 8 mA		9.4	9.9	10.4
I_VCP	Charge pump current capacity	VM > 12 V		12			mA
		8 V < VM < 12 V		10
		5.9 V < VM < 8 V		8
f_VCP⁽¹⁾	Charge pump switching frequency	VM > UVLO		200	400	700	kHz
CONTROL INPUTS (PH, EN, IN1, IN2, nSLEEP)
V_IL	Input logic low voltage					0.8	V
V_IH	Input logic high voltage			1.5			V
V_HYS	Input logic hysteresis			100			mV
I_IL	Input logic low current	V_IN = 0 V		–5		5	μA
I_IH	Input logic high current	V_IN = 5 V				78	μA
R_PD	Pulldown resistance			64	115	173	kΩ
t_PD	Propagation delay	PH/EN, IN1/IN2 to GHx/GLx			500		ns
CONTROL OUTPUTS (nFAULT, SNSOUT)
V_OL	Output logic low voltage	I_O = 2 mA				0.1	V
I_OZ	Output high impedance leakage	V_IN = 5 V		–2		2	μA
FET GATE DRIVERS (GH1, GH2, SH1, SH2, GL1, GL2)
V_GHS	High-side VGS gate drive (gate-to-source)	VM > 12 V; V_GHS with respect to SHx		8.5	9.5	10.5	V
		VM = 8 V; V_GHS with respect to SHx		5.5	6.4	7
		VM = 5.9 V; V_GHS with respect to SHx		3.5	4.0	4.5
V_GLS	Low-side VGS gate drive (gate-to-source)	VM > 12 V		8.5	9.3	10.5	V
V_GLS	Low-side VGS gate drive (gate-to-source)	VM = 5.9 V		3.9	4.3	4.9	V
t_DEAD	Output dead time	Observed t_DEAD depends on IDRIVE setting			380		ns
t_DRIVE	Gate drive time				2.5		μs
I_DRIVE,SRC	Peak source current	R_IDRIVE < 1 kΩ to GND			6		mA
		R_IDRIVE = 33 kΩ ±5% to GND			12.5
		R_IDRIVE = 200 kΩ ±5% to GND, or R_IDRIVE < 1 kΩ to AVDD			25
		R_IDRIVE > 500 kΩ ±5% to GND			100
		R_IDRIVE = 68 kΩ ±5% to AVDD			150
I_DRIVE,SNK	Peak sink current	R_IDRIVE < 1 kΩ to GND			12.5		mA
		R_IDRIVE = 33 kΩ ±5% to GND			25
		R_IDRIVE = 200 kΩ ±5% to GND			50
		R_IDRIVE < 1 kΩ to AVDD			200
		R_IDRIVE > 500 ±5% kΩ to GND			300
		R_IDRIVE = 68 kΩ ±5% to AVDD			50
I_HOLD	FET holding current	Source current after t_DRIVE			6		mA
I_HOLD	FET holding current	Sink current after t_DRIVE			25		mA
I_STRONG	FET hold-off strong pulldown	GHx			490		mA
I_STRONG	FET hold-off strong pulldown	GLx			690		mA
R_OFF	FET gate hold-off resistor	Pulldown GHx to SHx			200		kΩ
R_OFF	FET gate hold-off resistor	Pulldown GLx to GND			150		kΩ
CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF)
V_VREF	VREF input voltage	For current internal chopping		0.3⁽³⁾		AVDD	V
A_V	Amplifier gain	50 < V_SP < 200 mV; V_SN = GND		18	20	22	V/V
A_V	Amplifier gain	10 < V_SP < 50 mV; V_SN = GND		16	20	24	V/V
V_OFF	SO offset	V_SP = V_SN = GND			50	250	mV
I_SP	SP input current	V_SP = 100 mV; V_SN = GND			-40		μA
t_SET⁽²⁾	Settling time to ±1%	V_SP = V_SN = GND to V_SP = 100 mV, V_SN = GND				1.5	µs
C_SO⁽²⁾	Allowable SO pin capacitance					1	nF
t_OFF	PWM current regulation off-time				25		µs
t_BLANK	PWM blanking time				2		µs
PROTECTION CIRCUITS
V_UVLO	VM undervoltage lockout	VM falling; UVLO report			5.4	5.8	V
V_UVLO	VM undervoltage lockout	VM rising; UVLO recovery			5.6	5.9	V
V_UVLO,HYS	VM undervoltage hysteresis	Rising to falling threshold		100			mV
t_UVLO	VM UVLO falling deglitch time	VM falling; UVLO report			10		μs
V_CPUV	Charge pump undervoltage	CPUV report			VM + 2.8		V
V_{DS OCP}	Overcurrent protection trip level, VDS of each external FET	High-side FETs: VM – SHx Low-side FETs: SHx – SP		0.8	1		V
V_{SP OCP}	Overcurrent protection trip level, measured by sense amplifier	V_SP voltage with respect to GND		0.8	1		V
t_OCP	Overcurrent deglitch time				4.5		µs
t_RETRY	Overcurrent retry time				3		ms
T_TSD⁽²⁾	Thermal shutdown temperature	Die temperature, T_J		150			°C
T_HYS⁽²⁾	Thermal shutdown hysteresis	Die temperature, T_J			20		°C
V_{GS CLAMP}	Gate drive clamping voltage	Positive clamping voltage		10.5		13	V
V_{GS CLAMP}	Gate drive clamping voltage	Negative clamping voltage		–1	–0.7	–0.5	V