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ZHCSQL7F May 2010 – May 2022 DRV8312 , DRV8332

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

DKD|36
- MPDS126L

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6.7 Electrical Characteristics

T_A = 25°C, PVDD = 50 V, GVDD = VDD = 12 V, f_Sw = 400 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise specified.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
V_REG	Voltage regulator, only used as a reference node	VDD = 12 V	2.95	3.3	3.65	V
I_VDD	VDD supply current	Idle, reset mode		9	12	mA
I_VDD	VDD supply current	Operating, 50% duty cycle		10.5
I_{GVDD_X}	Gate supply current per half-bridge	Reset mode		1.7	2.5	mA
I_{GVDD_X}	Gate supply current per half-bridge	Operating, 50% duty cycle		8
I_{PVDD_X}	Half-bridge X (A, B, or C) idle current	Reset mode		0.7	1	mA
OUTPUT STAGE
R_DS(on)	MOSFET drain-to-source resistance, low side (LS)	T_J = 25°C, GVDD = 12 V		80		m?
R_DS(on)	MOSFET drain-to-source resistance, high side (HS)	T_J = 25°C, GVDD = 12 V		80		m?
V_F	Diode forward voltage drop	T_J = 25°C - 125°C, I_O = 5 A		1		V
t_R	Output rise time	Resistive load, I_O = 5 A		14		ns
t_F	Output fall time	Resistive load, I_O = 5 A		14		ns
t_{PD_ON}	Propagation delay when FET is on	Resistive load, I_O = 5 A		38		ns
t_{PD_OFF}	Propagation delay when FET is off	Resistive load, I_O = 5 A		38		ns
t_DT	Dead time between HS and LS FETs	Resistive load, I_O = 5 A		5.5		ns
I/O PROTECTION
V_uvp,G	Gate supply voltage GVDD_X undervoltage protection threshold			8.5		V
V_uvp,hyst⁽¹⁾	Hysteresis for gate supply undervoltage event			0.8		V
OTW⁽¹⁾	Overtemperature warning		115	125	135	°C
OTW_hyst⁽¹⁾	Hysteresis temperature to reset OTW event			25		°C
OTSD⁽¹⁾	Overtemperature shut down			150		°C
OTE-OTW_differential⁽¹⁾	OTE-OTW overtemperature detect temperature difference			25		°C
OTSD_HYST⁽¹⁾	Hysteresis temperature for FAULT to be released following an OTSD event			25		°C
I_OC	Overcurrent limit protection	Resistor—programmable, nominal, R_OCP = 27 k?		9.7		A
I_OCT	Overcurrent response time	Time from application of short condition to Hi-Z of affected FET(s)		250		ns
STATIC DIGITAL SPECIFICATIONS
V_IH	High-level input voltage	PWM_A, PWM_B, PWM_C, M1, M2, M3	2		3.6	V
V_IH	High-level input voltage	RESET_A, RESET_B, RESET_C	2		3.6	V
V_IL	Low-level input voltage	PWM_A, PWM_B, PWM_C, M1, M2, M3, RESET_A, RESET_B, RESET_C			0.8	V
l_lkg	Input leakage current		-100		100	μA
OTW / FAULT
R_{INT_PU}	Internal pullup resistance, OTW to VREG, FAULT to VREG		20	26	35	k?
V_OH	High-level output voltage	Internal pullup resistor only	2.95	3.3	3.65	V
V_OH	High-level output voltage	External pullup of 4.7 k? to 5 V	4.5		5	V
V_OL	Low-level output voltage	I_O = 4 mA		0.2	0.4	V

(1) Specified by design