6 Pin Configuration and Functions

Figure 6-1 DRV8317S 36-Pin WQFN With Exposed Thermal Pad Top View

Figure 6-2 DRV8317H 36-Pin WQFN With Exposed Thermal Pad Top View

Table 6-1 Pin Functions

PIN	36-pin package		TYPE^⁽¹⁾	DESCRIPTION
NAME	DRV8317S	DRV8317H	TYPE^⁽¹⁾	DESCRIPTION
AGND	21	21	GND	Device analog ground. Connect to a separate ground plane.^²
AVDD	22	22	PWR O	3.3V regulator output. Connect a X5R or X7R, 2.2-μF (no load) or 4.7-μF (up to 80mA load), 6.3-V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 80 mA for external loads.
CP	6	6	PWR	Charge pump output. Connect a X5R or X7R, 1-μF, 16-V ceramic capacitor between the CP and VM pins.
CPH	5	5	PWR	Charge pump switching node. Connect a X5R or X7R, 100-nF, (2xVM)- rated ceramic capacitor between the CPH and CPL pins.
CPL	4	4	PWR
CSAREF	33	33	PWR I	Current sense amplifier power supply input/reference. Connect a X5R or X7R, 0.1-μF, 6.3-V ceramic capacitor between the CSAREF and AGND pins.
GAIN	—	29	I	Available only in hardware variant (DRV8317H). The pin is a 4-level input pin for current sense amplifier gain setting.
INHA	23	23	I	High-side driver control input for OUTA. This pin controls the state of the high-side MOSFET in 6x/3x PWM Mode.
INHB	25	25	I	High-side driver control input for OUTB. This pin controls the state of the high-side MOSFET in 6x/3x PWM Mode.
INHC	27	27	I	High-side driver control input for OUTC. This pin controls the state of the high-side MOSFET in 6x/3x PWM Mode.
INLA	24	24	I	Low-side driver control input for OUTA. This pin controls the state of the low-side MOSFET in 6x PWM Mode.
INLB	26	26	I	Low-side driver control input for OUTB. This pin controls the state of the low-side MOSFET in 6x PWM Mode.
INLC	28	28	I	Low-side driver control input for OUTC. This pin controls the state of the low-side MOSFET in 6x PWM Mode.
MODE	—	31	I	Available only in hardware variant (DRV8317H). This is a 4-level input pin for PWM mode setting.
NC	3	3, 32	—	No connect. Leave the pin floating.
nFAULT	2	2	O	Fault indication pin. Pulled low during fault condition. Open-drain output; requires an external pull-up resistor to AVDD.
nSCS	32	—	I	Available only in SPI variant (DRV8317S). Serial chip select. A logic low on this pin enables serial interface communication.
nSLEEP	1	1	I	When this pin is logic low the device goes to a low-power sleep mode. A 15 to 50-μs low pulse on nSLEEP pin can be used to reset fault conditions without entering sleep mode.
OUTA	11, 12	11, 12	O	Half-bridge output A. Connect to motor winding.
OUTB	14, 15	14, 15	O	Half-bridge output B. Connect to motor winding.
OUTC	17, 18	17, 18	O	Half-bridge output C. Connect to motor winding.
PGND	10, 13, 16, 19	10, 13, 16, 19	PWR	Device power ground. Connect to a separate ground plane.^²
SCLK	31	—	I	Available only in SPI variant (DRV8317S). Serial clock input. Serial data is shifted out on the rising edge and captured on the falling edge of SCLK.
SDI	30	—	I	Available only in SPI variant (DRV8317S). Serial data input. Data (input) is captured on the falling edge of the SCLK pin (SPI devices).
SDO	29	—	O	Available only in SPI variant (DRV8317S). Serial data output. Data (output) is shifted out on the rising edge of the SCLK pin.
SLEW	—	30	I	Available only in hardware variant (DRV8317H). This pin is a 4-level input pin for OUTx voltage slew rate setting.
SOA	36	36	O	Current sense amplifier output for OUTA.
SOB	35	35	O	Current sense amplifier output for OUTB.
SOC	34	34	O	Current sense amplifier output for OUTC.
VIN_AVDD	7	7	PWR	Input supply for AVDD LDO
VM	8, 9, 20	8, 9, 20	PWR	Device and motor power supply. Connect to motor supply voltage; bypass to PGND with a 0.1-μF capacitor plus one bulk capacitor. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device
Thermal pad			PWR	Must be connected to AGND.

(1) I = input, O = output, PWR = power, GND = ground, NC = no connect