ZHCSN76B January 2021 – April 2022 DRV8316
PRODUCTION DATA
The buck regulator implements a pulse frequency modulation (PFM) architecture with peak current mode control. The output voltage of the buck regulator is compared with the internal reference voltage (VBK_REF) which is internally generated depending on the buck-output voltage setting (BUCK_SEL) which constitutes an outer voltage control loop. Depending on the comparator output going high (VBK < VBK_REF) or low (VBK > VBK_REF), the high-side power FET of the buck turns on and turna off respectively. An independent current control loop monitors the current in high-side power FET (IBK) and turns off the high-side FET when the current becomes higher than the buck current limit (IBK_CL). This implements a current limit control for the buck regulator. Figure 8-12 shows the architecture of the buck and various control/protection loops.