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ZHCSBP4C September 2013 – December 2016 DRV8303

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

DCA|48
- MPDS044E

散熱焊盤機械數據 (封裝 | 引腳)

DCA|48
- PPTD085M

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_PVDD	Supply voltage	Relative to PGND	–0.3	65	V
V_PVDD	Maximum supply-voltage ramp rate	Voltage rising up to PVDD_MAX		1	V/µs
V_PGND	Maximum voltage between PGND and GND		–0.3	0.3	V
V_{OPA_IN}	Voltage for SPx and SNx pins		–0.6	0.6	V
V_LOGIC	Input voltage for logic and digital pins (INH_A, INL_A, INH_B, INL_B, INH_C, INL_C, EN_GATE, SCLK, SDI, SCS, DC_CAL)		–0.3	7	V
V_GVDD	Maximum voltage for GVDD pin			13.2	V
V_AVDD	Maximum voltage for AVDD pin			8	V
V_DVDD	Maximum voltage for DVDD pin			3.6	V
V_{VDD_SPI}	Maximum voltage for VDD_SPI pin			7	V
V_SDO	Maximum voltage for SDO pin			V_{DD_SPI} +0.3	V
V_REF	Maximum reference voltage for current amplifier			7	V
V_{BST_MAX}	Maximum voltage for BST_X Pin		–0.3	80	V
V_{BST_DIFF}	Maximum voltage difference for (BST_X-SH_X) and (BST_X-GH_X)		–0.3	14.5	V
V_{GH_MAX}	Maximum voltage for GH_X pin		–0.3	80	V
V_{GH_DIF}	Maximum voltage difference for (GH_X-SH_X)		–0.3	14.5	V
V_{GL_MAX}	Maximum voltage for GL_X pin		–0.3	13.2	V
V_{GL_DIF}	Maximum voltage difference for (GL_X-SL_X)		–0.3	13.2	V
V_{SH_MAX}	Maximum voltage for SH_X pin		–2	PVDD + 2	V
V_{SL_MAX}	Maximum voltage for SL_X pin		–0.6	0.6	V
I_{IN_MAX}	Maximum current for all digital and analog inputs (INH_A, INL_A, INH_B, INL_B, INH_C, INL_C, SCLK, SCS, SDI, EN_GATE, DC_CAL, DTC)		–1	1	mA
I_{SINK_MAX}	Maximum sinking current for open-drain pins (nFAULT and nOCTW pins)			7	mA
I_REF	Maximum current for REF pin		100		µA
T_stg	Storage temperature		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE		UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000		V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500		V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted).

			MIN	MAX	UNIT
V_PVDD	DC supply voltage PVDD for normal operation	Relative to PGND	6	60	V
I_{DIN_EN}	Input current of digital pins when EN_GATE is high			100	µA
I_{DIN_DIS}	Input current of digital pins when EN_GATE is low			1	µA
C_{O_OPA}	Maximum output capacitance on outputs of shunt amplifier			20	pF
R_DTC	Dead time control resistor. Time range is 50 ns (–GND) to 500 ns (150 kΩ) with a linear approximation.		0	150	kΩ
I_FAULT	nFAULT pin sink current. Open drain	V = 0.4 V		2	mA
I_OCTW	nOCTW pin sink current. Open drain	V = 0.4 V		2	mA
V_REF	External voltage reference voltage for current shunt amplifiers		2	6	V
f_gate	Operating switching frequency of gate driver	Q_g(TOT) = 25 nC or total 30-mA gate drive average current		200	kHz
I_gate	Total average gate drive current			30	mA
T_A	Ambient temperature		–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DRV8303	UNIT
		DCA (TSSOP)
		48 PINS
R_θJA	Junction-to-ambient thermal resistance	30.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	33.5	°C/W
R_θJB	Junction-to-board thermal resistance	17.5	°C/W
ψ_JT	Junction-to-top characterization parameter	0.9	°C/W
ψ_JB	Junction-to-board characterization parameter	7.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

PVDD = 6 V to 60 V, T_C = 25°C, unless specified under test condition

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT PINS: INH_X, INL_X, SCS, SDI, SCLK, EN_GATE, DC_CAL
V_IH	High input threshold		2			V
V_IL	Low input threshold				0.8	V
RPULL_DOWN – INTERNAL PULLDOWN RESISTOR FOR GATE DRIVER INPUTS
R_{EN_GATE}	Internal pulldown resistor for EN_GATE			100		kΩ
R_{INH_X}	Internal pulldown resistor for high side PWMs (INH_A, INH_B, and INH_C)	EN_GATE high		100		kΩ
R_{INH_X}	Internal pulldown resistor for low side PWMs (INL_A, INL_B, and INL_C)	EN_GATE high		100		kΩ
R_SCS	Internal pulldown resistor for nSCS	EN_GATE high		100		kΩ
R_SDI	Internal pulldown resistor for SDI	EN_GATE high		100		kΩ
R_{DC_CAL}	Internal pulldown resistor for DC_CAL	EN_GATE high		100		kΩ
R_SCLK	Internal pulldown resistor for SCLK	EN_GATE high		100		kΩ
OUTPUT PINS: nFAULT AND nOCTW
V_OL	Low-output threshold	I_O = 2 mA			0.4	V
V_OH	High-output threshold	External 47-kΩ pullup resistor connected to 3-5.5 V	2.4			V
I_OH	Leakage current on open drain pins when logic high (nFAULT and nOCTW)				1	µA
GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C
V_{GX_NORM}	Gate driver Vgs voltage	PVDD = 8V to 60 V, I_gate = 30 mA, C_CP = 22 nF	9.5		11.5	V
V_{GX_NORM}	Gate driver Vgs voltage	PVDD = 8 V to 60 V, I_gate = 30 mA, C_CP = 220 nF	9.5		11.5	V
V_{GX_MIN}	Gate driver Vgs voltage	PVDD = 6 V to 8 V, I_gate = 15 mA, C_CP = 22 nF	8.8			V
V_{GX_MIN}	Gate driver Vgs voltage	PVDD = 6 V to 8 V, I_gate = 30 mA, C_CP = 220 nF	8.3			V
I_oso1	Maximum source current setting 1, peak	Vgs of FET equals to 2 V. REG 0x02		1.7		A
I_osi1	Maximum sink current setting 1, peak	Vgs of FET equals to 8 V. REG 0x02		2.3		A
I_oso2	Source current setting 2, peak	Vgs of FET equals to 2 V. REG 0x02		0.7		A
I_osi2	Sink current setting 2, peak	Vgs of FET equals to 8 V. REG 0x02		1		A
I_oso3	Source current setting 3, peak	Vgs of FET equals to 2 V. REG 0x02		0.25		A
I_osi3	Sink current setting 3, peak	Vgs of FET equals to 8 V. REG 0x02		0.5		A
R_{gate_off}	Gate output impedance during standby mode when EN_GATE low (pins GH_x, GL_x)		1.6		2.4	kΩ
SUPPLY CURRENTS
I_{PVDD_STB}	PVDD supply current, standby	EN_GATE is low. PVDD = 8 V		20	50	µA
I_{PVDD_OP}	PVDD supply current, operating	EN_GATE is high, no load on gate drive output, switching at 10 kHz, 100-nC gate charge		15		mA
I_{PVDD_HIZ}	PVDD supply current, Hi-Z	EN_GATE is high, gate not switching	2	5	10	mA
INTERNAL REGULATOR VOLTAGE
A_VDD	AVDD voltage	PVDD = 8 V to 60 V	6	6.5	7	V
A_VDD	AVDD voltage	PVDD = 6 V to 8 V	5.5		6	V
D_VDD	DVDD voltage		3	3.3	3.6	V
VOLTAGE PROTECTION
V_{PVDD_UV}	Undervoltage protection limit, PVDD				6	V
V_{GVDD_UV}	Undervoltage protection limit, GVDD				7.5	V
V_{GVDD_OV}	Overvoltage protection limit, GVDD			16		V
CURRENT PROTECTION, (VDS SENSING)
V_{DS_OC}	Drain-source voltage protection limit	PVDD = 8 V to 60 V	0.125		2.4	V
V_{DS_OC}	Drain-source voltage protection limit	PVDD = 6 V to 8 V⁽¹⁾	0.125		1.491	V
T_OC	OC sensing response time			1.5		µs
T_{OC_PULSE}	nOCTW pin reporting pulse stretch length for OC event			64		µs
TEMPERATURE PROTECTION
OTW_CLR	Junction temperature for resetting over temperature warning			115		°C
OTW_SET/ OTSD_CLR	Junction temperature for over temperature warning and resetting over temperature shut down			130		°C
OTSD_SET	Junction temperature for over temperature shut down		150			°C

(1) Reduced A_VDD voltage range results in limitations on settings for overcurrent protection. See Table 12.

6.6 Current Shunt Amplifier Characteristics

Over operating free-air temperature range.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
G1	Gain option 1	Tc = –40°C to 125°C	9.5	10	10.5	V/V
G2	Gain option 2	Tc = –40°C to 125°C	18	20	21	V/V
G3	Gain Option 3	Tc = –40°C to 125°C	38	40	42	V/V
G4	Gain Option 4	Tc = –40°C to 125°C	75	80	85	V/V
Tsettling	Settling time to 1%	Tc = 0 to 60°C, G = 10, Vstep = 2 V		300		ns
Tsettling	Settling time to 1%	Tc = 0 to 60°C, G = 20, Vstep = 2 V		600		ns
Tsettling	Settling time to 1%	Tc = 0 to 60°C, G = 40, Vstep = 2 V		1.2		µs
Tsettling	Settling time to 1%	Tc = 0 to 60°C, G = 80, Vstep = 2 V		2.4		µs
Vswing	Output swing linear range		0.3		5.7	V
	Slew Rate	G = 10		10		V/µs
DC_offset	Offset error RTI	G = 10 with input shorted			4	mV
Drift_offset	Offset drift RTI			10		µV/C
Ibias	Input bias current				100	µA
Vin_com	Common input mode range		–0.15		0.15	V
Vin_dif	Differential input range		–0.3		0.3	V
Vo_bias	Output bias	With zero input current, V_REF up to 6 V	–0.5%	0.5×Vref	0.5%	V
CMRR_OV	Overall CMRR with gain resistor mismatch	CMRR at DC, gain = 10	70	85		dB

6.7 SPI Characteristics (Slave Mode Only)

			MIN	NOM	MAX	UNIT
t_{SPI_READY}	SPI ready after EN_GATE transitions to HIGH	PVDD > 6 V		5	10	ms
t_CLK	Minimum SPI clock period		100			ns
t_CLKH	Clock high time	See Figure 1	40			ns
t_CLKL	Clock low time	See Figure 1	40			ns
t_{SU_SDI}	SDI input data setup time		20			ns
t_{HD_SDI}	SDI input data hold time		30			ns
t_{D_SDO}	SDO output data delay time, CLK high to SDO valid	C_L = 20 pF			20	ns
t_{HD_SDO}	SDO output data hold time	See Figure 1	40			ns
t_{SU_SCS}	SCS setup time	See Figure 1	50			ns
t_{HD_SCS}	SCS hold time		50			ns
t_{HI_SCS}	SCS minimum high time before SCS active low		40			ns
t_ACC	SCS access time, SCS low to SDO out of high impedance			10		ns
t_DIS	SCS disable time, SCS high to SDO high impedance			10		ns

6.8 Gate Timing and Protection Switching Characteristics

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
TIMING, OUTPUT PINS
t_pd,If-O	Positive input falling to GH_x falling	C_L = 1 nF, 50% to 50%		45		ns
t_pd,Ir-O	Positive input rising to GL_x falling	C_L = 1 nF, 50% to 50%		45		ns
t_{d_min}	Minimum dead time after hand shaking⁽¹⁾				50	ns
t_dtp	Dead time	With R_DTC set to different values	50		500	ns
t_GDr	Rise time, gate drive output	C_L = 1 nF, 10% to 90%		25		ns
t_GDF	Fall time, gate drive output	C_L = 1 nF, 90% to 10%		25		ns
t_{ON_MIN}	Minimum on pulse	Not including handshake communication. Hi-Z to on state, output of gate driver			50	ns
t_{pd_match}	Propagation delay matching between high side and low side				5	ns
t_{dt_match}	Deadtime matching				5	ns
TIMING, PROTECTION AND CONTROL
t_{pd,R_GATE-OP}	Start-up time, from EN_GATE active high to device ready for normal operation	PVDD is up before start up, all charge pump caps and regulator capacitors as in the Recommended Operating Conditions		5	10	ms
t_{pd,R_GATE-Quick}	If EN_GATE goes from high to low and back to high state within quick reset time, it will only reset all faults and gate driver without powering down charge pump, current amp, and related internal voltage regulators.	Maximum low pulse time			10	µs
t_pd,E-L	Delay, error event to all gates low			200		ns
t_pd,E-FAULT	Delay, error event to FAULT low			200		ns

(1) Dead time programming definition: Adjustable delay from GH_x falling edge to GL_X rising edge, and GL_X falling edge to GH_X rising edge. This is a minimum dead-time insertion. It is not added to the value set by the microcontroller externally.

Figure 1. SPI Slave Mode Timing Definition

Figure 2. SPI Slave Mode Timing Diagram

6.9 Typical Characteristics

PVDD = 8 V

EN_GATE = LOW

Figure 3. I_PVDD1 vs Temperature

PVDD = 60 V

EN_GATE = HIGH

Figure 5. GVDD vs Temperature

PVDD = 8 V

EN_GATE = HIGH

Figure 4. GVDD vs Temperature