ZHCSBP4C September 2013 – December 2016 DRV8303
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Current Shunt Amplifier Characteristics
- 6.7 SPI Characteristics (Slave Mode Only)
- 6.8 Gate Timing and Protection Switching Characteristics
- 6.9 Typical Characteristics
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DCA|48
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DCA|48
訂購(gòu)信息
7 Detailed Description
7.1 Overview
The DRV8303 is a 6-V to 60-V, gate driver IC for three-phase motor drive applications. This device reduces external component count by integrating three half-bridge drivers and two current shunt amplifiers. The DRV8303 provides overcurrent, over-temperature, and undervoltage protection. Fault conditions are indicated through the nFAULT and nOCTW pins in addition to the SPI registers.
Adjustable dead time control and peak gate drive current allows for finely tuning the switching of the external MOSFETs. Internal hand shaking is used to prevent through current.
VDS sensing of the external MOSFETs allows for the DRV8303 to detect overcurrent conditions and respond appropriately. Individual MOSFET overcurrent conditions are reported through the SPI status registers.
7.2 Functional Block Diagram
7.3 Feature Description
The following sections describe the DRV8303 features.
7.3.1 Three-Phase Gate Driver
The half-bridge drivers use a bootstrap configuration with a trickle charge pump to support 100% duty cycle operation. Each half-bridge is configured to drive two N-channel MOSFETs, one for the high-side and one for the low-side. The half-bridge drivers can be used in combination to drive a 3-phase motor or separately to drive various other loads.
The peak gate drive current and internal dead times are adjustable to accommodate a variety of external MOSFETs and applications. The peak gate drive current is set through a register setting and the dead time is adjusted with an external resistor on the DTC pin. Shorting the DTC pin to ground will provide the minimum dead time (50 ns). There is an internal hand shake between the high side and low side MOSFETs during switching transitions to prevent current shoot through.
The three-phase gate driver can provide up to 30 mA of average gate drive current. This will support switching frequencies up to 200 kHz when the MOSFET Qg = 25 nC.
Each MOSFET gate driver has a VDS sensing circuit for overcurrent protection. The sense circuit measures the voltage from the drain to the source of the external MOSFETs while the MOSFET is enabled. This voltage is compared against the programmed trip point to determine if an overcurrent event has occurred. The high-side sense is between the PVDD1 and SH_X pins. The low-side sense is between the SH_X and SL_X pins. Ensuring a differential, low impedance connection to the external MOSFETs for these lines will help provide accurate VDS sensing.
The DRV8303 allows for both 6-PWM and 3-PWM control through a register setting.
Table 1. 6-PWM Mode
| INL_X | INH_X | GL_X | GH_X |
|---|---|---|---|
| 0 | 0 | L | L |
| 0 | 1 | L | H |
| 1 | 0 | H | L |
| 1 | 1 | L | L |
Table 2. 3-PWM Mode
| INL_X | INH_X | GL_X | GH_X |
|---|---|---|---|
| X | 0 | H | L |
| X | 1 | L | H |
Table 3. Gate Driver External Components
| NAME | PIN 1 | PIN 2 | RECOMMENDED |
|---|---|---|---|
| RnOCTW | nOCTW | VCC (1) | ≥10 kΩ |
| RnFAULT | nFAULT | VCC (1) | ≥10 kΩ |
| RDTC | DTC | GND (PowerPAD) | 0 to 150 kΩ (50 ns to 500 ns) |
| CGVDD | GVDD | GND (PowerPAD) | 2.2-µF (20%) ceramic, ≥ 16 V |
| CCP | CP1 | CP2 | 0.022-µF (20%) ceramic, rated for PVDD |
| CDVDD | DVDD | AGND | 1-µF (20%) ceramic, ≥ 6.3 V |
| CAVDD | AVDD | AGND | 1-µF (20%) ceramic, ≥ 10 V |
| CPVDD | PVDD | GND (PowerPAD) | ≥4.7-µF (20%) ceramic, rated for PVDD |
| CBST_X | BST_X | SH_X | 0.1-µF (20%) ceramic, ≥ 16 V |
7.3.2 Current Shunt Amplifiers
The DRV8303 includes two high performance current shunt amplifiers to accurate low-side, inline current measurement.
The current shunt amplifiers have 4 programmable GAIN settings through the SPI registers. These are 10, 20, 40, and 80 V/V.
They provide output offset up to 3 V to support bidirectional current sensing. The offset is set to half the voltage on the reference pin (REF).
To minimize DC offset and drift over temperature a calibration method is provided through either the DC_CAL pin or SPI register. When DC calibration is enabled, the device will short the input of the current shunt amplifier and disconnect the load. DC calibration can be done at any time, even during MOSFET switching, because the load is disconnected. For the best results, perform the DC calibration during the switching OFF period, when no load is present, to reduce the potential noise impact to the amplifier.
Use Equation 1 to calculate the output of the current shunt amplifier.
where
- VREF is the reference voltage (REF pin)
- G is the gain of the amplifier (10, 20, 40, or 80 V/V)
- SNX and SPx are the inputs of channel x. SPx should connect to the ground side of the sense resistor for the nest common mode rejection.
Figure 6 shows the simplified block diagram for the current shunt amplifier.
Figure 6. Current Shunt Amplifier Simplified Block Diagram
7.3.3 Protection Features
The DRV8303 provides a broad range of protection features and fault condition reporting. The DRV8303 has undervoltage and over-temperature protection for the IC. It also has overcurrent and undervoltage protection for the MOSFET power stage. In fault shut down conditions all gate driver outputs will be held low to ensure the external MOSFETs are in a high impedance state.
7.3.3.1 Power Stage Protection
The DRV8303 provides over-current and undervoltage protection for the MOSFET power stage. During fault shut down conditions, all gate driver outputs will be kept low to ensure external FETs at high impedance state.
7.3.3.2 Overcurrent Protection (OCP) and Reporting
To protect the power stage from damage due to excessive currents, VDS sensing circuitry is implemented in the DRV8303. Based on the RDS(on) of the external MOSFETs and the maximum allowed IDS, a voltage threshold can be determined to trigger the overcurrent protection features when exceeded. The voltage threshold is programmed through the SPI registers. Overcurrent protection should be used as a protection scheme only; it is not intended as a precise current regulation scheme. There can be up to a 20% tolerance across channels for the VDS trip point.
The VDS sense circuit measures the voltage from the drain to the source of the external MOSFET while the MOSFET is enabled. The high-side sense is between the PVDD and SH_X pins. The low-side sense is between the SH_X and SL_X pins. Ensuring a differential, low impedance connection to the external MOSFETs for these lines will help provide accurate VDS sensing .
There are four different overcurrent modes (OC_MODE) that can be set through the SPI registers. The OC status bits operate in latched mode. When an overcurrent condition occurs the corresponding OC status bit will latch in the DRV8303 registers until the fault is reset.
-
Current Limit Mode: In current limit mode the device uses current limiting instead of device shutdown during an overcurrent event. In this mode the device reports overcurrent events through the nOCTW pin. The nOCTW pin will be held low for a maximum 64-µs period (internal timer) or until the next PWM cycle. If another overcurrent event is triggered from another MOSFET, during a previous overcurrent event, the reporting will continue for another 64-µs period (internal timer will restart) or until both PWM signals cycle. The associated status bit will be asserted for the MOSFET in which the overcurrent was detected. There are two current control settings in current limit mode. These are set by one bit in the SPI registers. The default mode is cycle by cycle (CBC).
- Cycle-By-Cycle Mode (CBC): In CBC mode, the MOSFET on which overcurrent has been detected on will shut off until the next PWM cycle.
- Off-Time Control Mode: In Off-Time mode, the MOSFET in which overcurrent has been detected is disabled for a 64-µs period (set by internal timer). If overcurrent is detected in another MOSFET, the timer will be reset for another 64-µs period and both MOSFETs will be disabled for the duration. During this period, normal operation can be restored for a specific MOSFET with a corresponding PWM cycle.
- OC Latch Shut Down Mode: When an overcurrent event occurs, both the high-side and low-side MOSFETs will be disabled in the corresponding half-bridge. The nFAULT pin, nFAULT status bit, and OC status bit for the MOSFET in which the overcurrent was detected will latch until the fault is reset through the GATE_RESET bit or a quick EN_GATE reset pulse.
- Report Only Mode: No protective action will be taken in this mode when an overcurrent event occurs. The overcurrent event will be reported through the nOCTW pin (64-µs pulse) and SPI status register. The external MCU should take action based on its own control algorithm.
- OC Disable Mode: The device will ignore and not report all overcurrent detections.
7.3.3.3 Undervoltage Protection (UVLO)
To protect the power output stage during start-up, shutdown, and other possible undervoltage conditions, the DRV8303 provides undervoltage protection by driving the gate drive outputs (GH_X, GL_X) low whenever PVDD or GVDD are below their undervoltage thresholds (PVDD_UV/GVDD_UV). This will put the external MOSFETs in a high impedance state. When the device is in PVDD_UV it will not respond to SPI commands and the SPI registers will revert to their default settings.
A specific PVDD undervoltage transient brownout from 13 to 15 µs can cause the DRV8303 to become unresponsive to external inputs until a full power cycle. The transient condition consists of having PVDD greater than the PVDD_UV level and then PVDD dropping below the PVDD_UV level for a specific period of 13 to 15 µs. Transients shorter or longer than 13 to 15 µs will not affect the normal operation of the undervoltage protection. Additional bulk capacitance can be added to PVDD to reduce undervoltage transients.
7.3.3.4 Overvoltage Protection (GVDD_OV)
The device will shut down both the gate driver and charge pump if the GVDD voltage exceeds the GVDD_OV threshold to prevent potential issues related to the GVDD pin or the charge pump (for example, short of external GVDD cap or charge pump). The fault is a latched fault and can only be reset through a reset transition on the EN_GATE pin.
7.3.3.5 Overtemperature Protection
A two-level over-temperature detection circuit is implemented:
- Level 1: overtemperature warning (OTW)
OTW is reported through nOCTW pin (over-current-temperature warning) for default setting. OCTW pin can be set to report OTW or OCW only through SPI command. See SPI Register section. - Level 2: overtemperature (OT) latched shut down of gate driver and charge pump (OTSD_GATE)
Fault will be reported to nFAULT pin. This is a latched shut down, so gate driver will not be recovered automatically even OT condition is not present anymore. An EN_GATE reset through pin or SPI (RESET_GATE) is required to recover gate driver to normal operation after temperature goes below a preset value, tOTSD_CLR.
SPI operation is still available and register settings will be remaining in the device during OTSD operation as long as PVDD is still within defined operation range.
7.3.3.6 Fault and Protection Handling
The nFAULT pin indicates an error event with shut down has occurred such as over-current, over-temperature, overvoltage, or undervoltage. Note that nFAULT is an open-drain signal. nFAULT will go high when gate driver is ready for PWM signal (internal EN_GATE goes high) during start up.
The nOCTW pin indicates overcurrent event and over temperature event that not necessary related to shut down.
Table 4 summarizes all protection features and their reporting structure:
Table 4. Fault and Warning Reporting and Handling
| EVENT | ACTION | LATCH | REPORTING ON nFAULT PIN |
REPORTING ON nOCTW PIN |
REPORTING IN SPI STATUS REGISTER |
|---|---|---|---|---|---|
| PVDD undervoltage |
External FETs HiZ; Weak pulldown of all gate driver output |
N | Y | N | Y |
| DVDD undervoltage |
External FETs HiZ; Weak pulldown of all gate driver output; When recovering, reset all status registers |
N | Y | N | N |
| GVDD undervoltage |
External FETs HiZ; Weak pulldown of all gate driver output |
N | Y | N | Y |
| GVDD overvoltage |
External FETs HiZ; Weak pulldown of all gate driver output Shut down the charge pump Won’t recover and reset through SPI reset command or quick EN_GATE toggling |
Y | Y | N | Y |
| OTW | None | N | N | Y (in default setting) | Y |
| OTSD_GATE | Gate driver latched shut down. Weak pulldown of all gate driver output to force external FETs HiZ Shut down the charge pump |
Y | Y | Y | Y |
| External FET overload – current limit mode |
External FETs current Limiting (only OC detected FET) |
N | N | Y | Y, indicates which phase has OC |
| External FET overload – Latch mode |
Weak pulldown of gate driver output and PWM logic “0” of LS and HS in the same phase. External FETs HiZ |
Y | Y | Y | Y |
| External FET overload – reporting only mode |
Reporting only | N | N | Y | Y, indicates which phase has OC |
7.3.4 Start-Up and Shutdown Sequence Control
During power up, all gate drive outputs are held low. Normal operation of gate driver and current shunt amplifiers can be initiated by toggling EN_GATE from a low state to a high state. If no errors are present, the DRV8303 is ready to accept PWM inputs. Gate driver always has control of the power FETs even in gate disable mode as long as PVDD is within functional region.
There is an internal diode from SDO to VDD_SPI, so VDD_SPI is required to be powered to the same power level as other SPI devices (if there is any SDO signal from other devices) all the time. VDD_SPI supply should be powered up first before any signal appears at SDO pin and powered down after completing all communications at SDO pin.
7.4 Device Functional Modes
7.4.1 EN_GATE
EN_GATE low is used to put gate driver, charge pump, current shunt amplifier, and internal regulator blocks into a low power consumption mode to save energy. SPI communication is not supported during this state. Device will put the MOSFET output stage to high impedance mode as long as PVDD is still present.
When EN_GATE pin goes to high, it will go through a power-up sequence, and enable gate driver, current amplifiers, charge pump, internal regulator, and so forth, and reset all latched faults related to gate driver block. It will also reset status registers in SPI table. All latched faults can be reset when EN_GATE is toggled after an error event unless the fault is still present.
When EN_GATE goes from high to low, it will shut down gate driver block immediately, so gate output can put external FETs in high impedance mode. It will then wait for 10us before completely shutting down the rest of the blocks. A quick fault reset mode can be done by toggling EN_GATE pin for a very short period (less than 10 µs). This will prevent device to shut down other function blocks such as charge pump and internal regulators and bring a quicker and simple fault recovery. SPI will still function with such a quick EN_GATE reset mode.
The other way to reset all the faults is to use SPI command (RESET_GATE), which will only reset gate driver block and all the SPI status registers without shutting down other function blocks.
One exception is to reset a GVDD_OV fault. A quick EN_GATE quick fault reset or SPI command reset does not work with GVDD_OV fault. A complete EN_GATE with low level holding longer than 10µS is required to reset GVDD_OV fault. TI highly recommends inspecting the system and board when GVDD_OV occurs.
7.4.2 DTC
Dead time can be programmed through DTC pin. A resistor should be connected from DTC to ground to control the dead time. Dead time control range is from 50 ns to 500 ns. Short DTC pin to ground will provide minimum dead time (50 ns). Resistor range is 0 kΩ to 150 kΩ. Dead time is linearly set over this resistor range.
Current shoot through prevention protection will be enabled in the device all time independent of dead time setting and input mode setting.
7.4.3 VDD_SPI
VDD_SPI is the power supply to power SDO pin. It must be connected to the same power supply (3.3V or 5V) that MCU uses for its SPI operation.
During power up or down transient, VDD_SPI pin could be zero voltage shortly. During this period, no SDO signal should be present at SDO pin from any other devices in the system because it causes a parasitic diode in the DRV8303 conducting from SDO to VDD_SPI pin as a short. This should be considered and prevented from system power sequence design.
7.4.4 DC_CAL
When DC_CAL is enabled, device will short inputs of shunt amplifier and disconnect from the load, so external microcontroller can do a DC offset calibration. DC offset calibration can be also done with SPI command. If using SPI exclusively for DC calibration, the DC_CAL pin can connected to GND.
7.5 Programming
7.5.1 SPI Communication
7.5.1.1 SPI
The DRV8303 SPI operates as a slave. The SPI input (SDI) data format consists of a 16 bit word with 1 read/write bit, 4 address bits, and 11 data bits. The SPI output (SDO) data format consists of a 16 bit word with 1 frame fault bit, 4 address bits, and 11 data bits. When a frame is not valid, frame fault bit will set to 1 and the remaining bits will shift out as 0.
A valid frame must meet following conditions:
- Clock must be low when nSCS goes low.
- Should have 16 full clock cycles.
- Clock must be low when nSCS goes high.
When nSCS is asserted high, any signals at the SCLK and SDI pins are ignored and SDO is forced into a high impedance state. When nSCS transitions from HIGH to LOW, SDO is enabled and the SDO response word loads into the shift register based on the previous SPI input word.
The SCLK pin must be low when nSCS transitions low. While nSCS is low, at each rising edge of the clock the response word is serially shifted out on the SDO pin with the MSB shifted out first.
While SCS is low, at each falling edge of the clock the new input word is sampled on the SDI pin. The SPI input word is decoded to determine the register address and access type (read or write). The MSB will be shifted in first. Any amount of time may pass between bits, as long as nSCS stays active low. This allows two 8-bit words to be used. If the input word sent to SDI is less than 16 bits or more than 16 bits, it is considered a frame error. If it is a write command, the data will be ignored. The fault bit in the next SDO response word will then report 1. After the 16th clock cycle or when nSCS transitions from LOW to HIGH, the SDI shift register data is transferred into a latch where the input word is decoded.
For a READ command (Nth cycle) sent to SDI, SDO will respond with the data at the specified address in the next cycle. (N+1)
For a WRITE command (Nth cycle) sent to SDI, SDO will respond with the data in Status Register 1 (0x00) in the next cycle (N+1). This feature is intended to maximize SPI communication efficiency when having multiple write commands.
7.5.1.2 SPI Format
The SDI input data word is 16 bits long and consists of:
- 1 read/write bit W [15]
- 4 address bits A [14:11]
- 11 data bits D [10:0]
The SDO output data word is 16 bits long and consists of:
- 1 fault frame bit F [15]
- 4 address bits A [14:11]
- 11 data bits D [10:0]
The SDO output word (Nth cycle) is in response to the previous SDI input word (N-1 cycle).
Therefore each SPI Query/Response pair requires two full 16 bit shift cycles to complete.
Table 5. SPI Input Data Control Word Format
| R/W | ADDRESS | DATA | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Word Bit | B15 | B14 | B13 | B12 | B11 | B10 | B9 | B8 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
| Command | W0 | A3 | A2 | A1 | A0 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
Table 6. SPI Output Data Response Word Format
| R/W | DATA | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Word Bit | B15 | B14 | B13 | B12 | B11 | B10 | B9 | B8 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
| Command | F0 | A3 | A2 | A1 | A0 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
7.6 Register Maps
7.6.1 Read / Write Bit
The MSB bit of the SDI input word (W0) is a read/write bit. When W0 = 0, the input word is a write command. When W0 = 1, input word is a read command.
7.6.2 Address Bits
Table 7. Register Address
| REGISTER TYPE | ADDRESS [A3..A0] | REGISTER NAME | DESCRIPTION | READ AND WRITE ACCESS | |||
|---|---|---|---|---|---|---|---|
| Status Register | 0 | 0 | 0 | 0 | Status Register 1 | Status register for device faults | R |
| 0 | 0 | 0 | 1 | Status Register 2 | Status register for device faults and ID | R | |
| Control Register | 0 | 0 | 1 | 0 | Control Register 1 | R/W | |
| 0 | 0 | 1 | 1 | Control Register 2 | R/W | ||
7.6.3 SPI Data Bits
7.6.3.1 Status Registers
Table 8. Status Register 1 (Address: 0x00) (all default values are zero)
| ADDRESS | REGISTER NAME | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | Status Register 1 | FAULT | GVDD_UV | PVDD_UV | OTSD | OTW | FETHA_OC | FETLA_OC | FETHB_OC | FETLB_OC | FETHC_OC | FETLC_OC |
Table 9. Status Register 2 (Address: 0x01) (all default values are zero)
| ADDRESS | REGISTER NAME | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x01 | Status Register 2 | GVDD_OV | Device ID [3] | Device ID [2] | Device ID [1] | Device ID [0] |
7.6.3.2 Control Registers
Table 10. Control Register 1 for Gate Driver Control (Address: 0x02)(1)
| ADDRESS | NAME | DESCRIPTION | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x02 | GATE_CURRENT | Gate drive peak current 1.7 A | 0(1) | 0(1) | |||||||||
| Gate drive peak current 0.7 A | 0 | 1 | |||||||||||
| Gate drive peak current 0.25 A | 1 | 0 | |||||||||||
| Reserved | 1 | 1 | |||||||||||
| GATE_RESET | Normal mode | 0(1) | |||||||||||
| Reset gate driver latched faults (reverts to 0) | 1 | ||||||||||||
| PWM_MODE | 6 PWM inputs (see Table 1) | 0(1) | |||||||||||
| 3 PWM inputs (see Table 2) | 1 | ||||||||||||
| OCP_MODE | Current limit | 0(1) | 0(1) | ||||||||||
| OC latch shut down | 0 | 1 | |||||||||||
| Report only | 1 | 0 | |||||||||||
| OC disabled | 1 | 1 | |||||||||||
| OC_ADJ_SET | See OC_ADJ_SET table | X | X | X | X | X |
Table 11. Control Register 2 for Current Shunt Amplifiers and Misc Control (Address: 0x03)(1)
| ADDRESS | NAME | DESCRIPTION | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x03 | OCTW_MODE | Report both OT and OC at nOCTW pin | 0(1) | 0(1) | |||||||||
| Report OT only | 0 | 1 | |||||||||||
| Report OC only | 1 | 0 | |||||||||||
| Report OC only (reserved) | 1 | 1 | |||||||||||
| GAIN | Gain of shunt amplifier: 10 V/V | 0(1) | 0(1) | ||||||||||
| Gain of shunt amplifier: 20 V/V | 0 | 1 | |||||||||||
| Gain of shunt amplifier: 40 V/V | 1 | 0 | |||||||||||
| Gain of shunt amplifier: 80 V/V | 1 | 1 | |||||||||||
| DC_CAL_CH1 | Shunt amplifier 1 connects to load through input pins | 0(1) | |||||||||||
| Shunt amplifier 1 shorts input pins and disconnects from load for external calibration | 1 | ||||||||||||
| DC_CAL_CH2 | Shunt amplifier 2 connects to load through input pins | 0(1) | |||||||||||
| Shunt amplifier 2 shorts input pins and disconnects from load for external calibration | 1 | ||||||||||||
| OC_TOFF | Cycle by cycle | 0(1) | |||||||||||
| Off-time control | 1 | ||||||||||||
| Reserved |
7.6.3.3 Overcurrent Adjustment
Table 12. OC_ADJ_SET Table
| Control Bit (D6–D10) (0xH) | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
| Vds (V) | 0.060 | 0.068 | 0.076 | 0.086 | 0.097 | 0.109 | 0.123 | 0.138 |
| Control Bit (D6–D10) (0xH) | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
| Vds (V) | 0.155 | 0.175 | 0.197 | 0.222 | 0.250 | 0.282 | 0.317 | 0.358 |
| Control Bit (D6–D10) (0xH) | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 |
| Vds (V) | 0.403 | 0.454 | 0.511 | 0.576 | 0.648 | 0.730 | 0.822 | 0.926 |
| Code Number (0xH) | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 |
| Vds (V) | 1.043 | 1.175 | 1.324 | 1.491 | 1.679(1) | 1.892(1) | 2.131(1) | 2.400(1) |