ZHCSMX4D September 2020 – March 2022 DRV8300
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER SUPPLIES (GVDD, BSTx) | ||||||
| IGVDD | GVDD standby mode current | INHx = INLX = 0; VBSTx = VGVDD | 400 | 800 | 1400 | μA |
| GVDD active mode current | INHx = INLX = Switching @20kHz; VBSTx = VGVDD; NO FETs connected | 400 | 825 | 1400 | μA | |
| ILBSx | Bootstrap pin leakage current | VBSTx = VSHx = 85V; VGVDD = 0V | 2 | 4 | 7 | μA |
| ILBS_TRAN | Bootstrap pin active mode transient leakage current | INHx = Switching@20kHz | 30 | 105 | 220 | μA |
| ILBS_DC | Bootstrap pin active mode leakage static current | INHx = High | 30 | 85 | 150 | μA |
| ILSHx | High-side source pin leakage current | INHx = INLX = 0; VBSTx - VSHx = 12V; VSHx = 0 to 85V | 30 | 55 | 80 | μA |
| LOGIC-LEVEL INPUTS (INHx, INLx, MODE) | ||||||
| VIL_MODE | Input logic low voltage | Mode pin | 0.6 | V | ||
| VIL | Input logic low voltage | INLx, INHx pins | 0.8 | V | ||
| VIH_MODE | Input logic high voltage | Mode pin | 3.7 | V | ||
| VIH | Input logic high voltage | INLx, INHx pins | 2.0 | V | ||
| VHYS_MODE | Input hysteresis | Mode pin | 1600 | 2000 | 2400 | mV |
| VHYS | Input hysteresis | INLx, INHx pins | 40 | 100 | 260 | mV |
| IIL_INLx | INLx Input logic low current | VPIN (Pin Voltage) = 0 V; INLx in non-inverting mode | -1 | 0 | 1 | μA |
| VPIN (Pin Voltage) = 0 V; INLx in inverting mode | 5 | 20 | 30 | μA | ||
| IIH_INLx | INLx Input logic high current | VPIN (Pin Voltage) = 5 V; INLx in non-inverting mode | 5 | 20 | 30 | μA |
| VPIN (Pin Voltage) = 5 V; INLx in inverting mode | 0 | 0.5 | 1.5 | μA | ||
| IIL | INHx, MODE Input logic low current | VPIN (Pin Voltage) = 0 V; | -1 | 0 | 1 | μA |
| IIH | INHx, MODE Input logic high current | VPIN (Pin Voltage) = 5 V; | 5 | 20 | 30 | μA |
| RPD_INHx | INHx Input pulldown resistance | To GND | 120 | 200 | 280 | kΩ |
| RPD_INLx | INLx Input pulldown resistance | To GND, INLx in non-inverting mode | 120 | 200 | 280 | kΩ |
| RPU_INLx | INLx Input pullup resistance | To INT_5V, INLx in inverting mode | 120 | 200 | 280 | kΩ |
| RPD_MODE | MODE Input pulldown resistance | To GND | 120 | 200 | 280 | kΩ |
| GATE DRIVERS (GHx, GLx, SHx, SLx) | ||||||
| VGHx_LO | High-side gate drive low level voltage | IGLx = -100 mA; VGVDD = 12V; No FETs connected | 0 | 0.15 | 0.35 | V |
| VGHx_HI | High-side gate drive high level voltage (VBSTx - VGHx) | IGHx = 100 mA; VGVDD = 12V; No FETs connected | 0.3 | 0.6 | 1.2 | V |
| VGLx_LO | Low-side gate drive low level voltage | IGLx = -100 mA; VGVDD = 12V; No FETs connected | 0 | 0.15 | 0.35 | V |
| VGLx_HI | Low-side gate drive high level voltage (VGVDD - VGHx) | IGHx = 100 mA; VGVDD = 12V; No FETs connected | 0.3 | 0.6 | 1.2 | V |
| IDRIVEP_HS | High-side peak source gate current | GHx-SHx = 12V | 400 | 750 | 1200 | mA |
| IDRIVEN_HS | High-side peak sink gate current | GHx-SHx = 0V | 850 | 1500 | 2100 | mA |
| IDRIVEP_LS | Low-side peak source gate current | GLx = 12V | 400 | 750 | 1200 | mA |
| IDRIVEN_LS | Low-side peak sink gate current | GLx = 0V | 850 | 1500 | 2100 | mA |
| tPD | Input to output propagation delay | INHx, INLx to GHx, GLx; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx | 70 | 125 | 180 | ns |
| tPD_match | Matching propagation delay per phase | GHx turning OFF to GLx turning ON, GLx turning OFF to GHx turning ON; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx | -30 | ±4 | 30 | ns |
| tPD_match | Matching propagation delay phase to phase | GHx/GLx turning ON to GHy/GLy turning ON, GHx/GLx turning OFF to GHy/GLy turning OFF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx | -30 | ±4 | 30 | ns |
| tR_GLx | GLx rise time (10% to 90%) | CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V | 10 | 24 | 50 | ns |
| tR_GHx | GHx rise time (10% to 90%) | CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V | 10 | 24 | 50 | ns |
| tF_GLx | GLx fall time (90% to 10%) | CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V | 5 | 12 | 30 | ns |
| tF_GHx | GHx fall time (90% to 10%) | CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V | 5 | 12 | 30 | ns |
| tDEAD | Gate drive dead time | DT pin floating | 150 | 215 | 280 | ns |
| DT pin connected to GND | 150 | 215 | 280 | ns | ||
| 40 k? between DT pin and GND | 150 | 200 | 260 | ns | ||
| 400 k? between DT pin and GND | 1500 | 2000 | 2600 | ns | ||
| tPW_MIN | Minimum input pulse width on INHx, INLx that changes the output on GHx, GLx | 40 | 70 | 150 | ns | |
| BOOTSTRAP DIODES (DRV8300D, DRV8300DI) | ||||||
| VBOOTD | Bootstrap diode forward voltage | IBOOT = 100 μA | 0.45 | 0.7 | 0.85 | V |
| IBOOT = 100 mA | 2 | 2.3 | 3.1 | V | ||
| RBOOTD | Bootstrap dynamic resistance (ΔVBOOTD/ΔIBOOT) | IBOOT = 100 mA and 80 mA | 11 | 15 | 25 | ? |
| PROTECTION CIRCUITS | ||||||
| VGVDDUV | Gate Driver Supply undervoltage lockout (GVDDUV) | Supply rising | 4.45 | 4.6 | 4.7 | V |
| Supply falling | 4.2 | 4.35 | 4.4 | V | ||
| VGVDDUV_HYS | Gate Driver Supply UV hysteresis | Rising to falling threshold | 250 | 280 | 310 | mV |
| tGVDDUV | Gate Driver Supply undervoltage deglitch time | 5 | 10 | 13 | μs | |
| VBSTUV | Boot Strap undervoltage lockout (VBSTx - VSHx) | Supply rising | 3.6 | 4.2 | 4.8 | V |
| Boot Strap undervoltage lockout (VBSTx - VSHx) | Supply falling | 3.5 | 4 | 4.5 | V | |
| VBSTUV_HYS | Bootstrap UV hysteresis | Rising to falling threshold | 200 | mV | ||
| tBSTUV | Bootstrap undervoltage deglitch time | 6 | 10 | 22 | μs | |