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ZHCSPF5 April 2022 DRV8300-Q1

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

PW|20
- MPDS362A

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

zhcspf5_oa

7.5 Electrical Characteristics

4.8 V ≤ V_GVDD ≤ 20 V, –40°C ≤ T_J≤ 150°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLIES (GVDD, BSTx)
I_GVDD	GVDD standby mode current	INHx = INLX = 0; V_BSTx = V_GVDD	400	800	1400	μA
I_GVDD	GVDD active mode current	INHx = INLX = Switching @20kHz; V_BSTx = V_GVDD; NO FETs connected	400	825	1400	μA
IL_BSx	Bootstrap pin leakage current	V_BSTx = V_SHx= 85V; V_GVDD = 0V	2	4	7	μA
IL_{BS_TRAN}	Bootstrap pin active mode transient leakage current	INHx = Switching@20kHz	30	105	220	μA
IL_{BS_DC}	Bootstrap pin active mode leakage static current	INHx = High	30	85	150	μA
IL_SHx	High-side source pin leakage current	INHx = INLX = 0; V_BSTx - V_SHx = 12V; V_SHx = 0 to 85V	30	55	80	μA
LOGIC-LEVEL INPUTS (INHx, INLx, MODE)
V_{HYS_MODE}	Input hysteresis	Mode pin	1600	2000	2400	mV
V_HYS	Input hysteresis	INLx, INHx pins	40	100	260	mV
I_{IL_INLx}	INLx Input logic low current	V_PIN(Pin Voltage) = 0 V; INLx in non-inverting mode	-1	0	1	μA
I_{IH_INLx}	INLx Input logic high current	V_PIN(Pin Voltage) = 5 V; INLx in non-inverting mode	5	20	30	μA
I_IL	INHx, MODE Input logic low current	V_PIN(Pin Voltage) = 0 V;	-1	0	1	μA
I_IH	INHx, MODE Input logic high current	V_PIN(Pin Voltage) = 5 V;	5	20	30	μA
R_{PD_INHx}	INHx Input pulldown resistance	To GND	120	200	280	kΩ
R_{PD_INLx}	INLx Input pulldown resistance	To GND, INLx in non-inverting mode	120	200	280	kΩ
R_{PD_MODE}	MODE Input pulldown resistance	To GND	120	200	280	kΩ
GATE DRIVERS (GHx, GLx, SHx, SLx)
V_{GHx_LO}	High-side gate drive low level voltage	I_GLx = -100 mA; V_GVDD= 12V; No FETs connected	0	0.15	0.35	V
V_{GHx_HI}	High-side gate drive high level voltage (V_BSTx- V_GHx)	I_GHx = 100 mA; V_GVDD= 12V; No FETs connected	0.3	0.6	1.2	V
V_{GLx_LO}	Low-side gate drive low level voltage	I_GLx = -100 mA; V_GVDD= 12V; No FETs connected	0	0.15	0.35	V
V_{GLx_HI}	Low-side gate drive high level voltage (V_GVDD- V_GHx)	I_GHx = 100 mA; V_GVDD= 12V; No FETs connected	0.3	0.6	1.2	V
I_{DRIVEP_HS}	High-side peak source gate current	GHx-SHx = 12V	400	750	1200	mA
I_{DRIVEN_HS}	High-side peak sink gate current	GHx-SHx = 0V	850	1500	2100	mA
I_{DRIVEP_LS}	Low-side peak source gate current	GLx = 12V	400	750	1200	mA
I_{DRIVEN_LS}	Low-side peak sink gate current	GLx = 0V	850	1500	2100	mA
t_PD	Input to output propagation delay	INHx, INLx to GHx, GLx; V_GVDD= V_BSTx - V_SHx> 8V; SHx = 0V, No load on GHx and GLx	70	125	180	ns
t_{PD_match}	Matching propagation delay per phase	GHx turning OFF to GLx turning ON, GLx turning OFF to GHx turning ON; V_GVDD= V_BSTx - V_SHx> 8V; SHx = 0V, No load on GHx and GLx	-30	±4	30	ns
t_{PD_match}	Matching propagation delay phase to phase	GHx/GLx turning ON to GHy/GLy turning ON, GHx/GLx turning OFF to GHy/GLy turning OFF; V_GVDD= V_BSTx - V_SHx> 8V; SHx = 0V, No load on GHx and GLx	-30	±4	30	ns
t_{R_GLx}	GLx rise time (10% to 90%)	C_LOAD= 1000 pF; V_GVDD= V_BSTx - V_SHx> 8V; SHx = 0V	10	24	50	ns
t_{R_GHx}	GHx rise time (10% to 90%)	C_LOAD= 1000 pF; V_GVDD= V_BSTx - V_SHx> 8V; SHx = 0V	10	24	50	ns
t_{F_GLx}	GLx fall time (90% to 10%)	C_LOAD= 1000 pF; V_GVDD= V_BSTx - V_SHx> 8V; SHx = 0V	5	12	30	ns
t_{F_GHx}	GHx fall time (90% to 10%)	C_LOAD= 1000 pF; V_GVDD= V_BSTx - V_SHx> 8V; SHx = 0V	5	12	30	ns
t_DEAD	Gate drive dead time		150	215	280	ns
t_{PW_MIN}	Minimum input pulse width on INHx, INLx that changes the output on GHx, GLx		40	70	150	ns
BOOTSTRAP DIODES (DRV8300D, DRV8300DI)
V_BOOTD	Bootstrap diode forward voltage	I_BOOT= 100 μA	0.45	0.7	0.85	V
V_BOOTD	Bootstrap diode forward voltage	I_BOOT= 100 mA	2	2.3	3.1	V
R_BOOTD	Bootstrap dynamic resistance (ΔV_BOOTD/ΔI_BOOT)	I_BOOT= 100 mA and 80 mA	11	15	25	?
PROTECTION CIRCUITS
V_GVDDUV	Gate Driver Supply undervoltage lockout (GVDDUV)	Supply rising	4.45	4.6	4.7	V
V_GVDDUV	Gate Driver Supply undervoltage lockout (GVDDUV)	Supply falling	4.2	4.35	4.4	V
V_{GVDDUV_HYS}	Gate Driver Supply UV hysteresis	Rising to falling threshold	250	280	310	mV
t_GVDDUV	Gate Driver Supply undervoltage deglitch time		5	10	13	μs
V_BSTUV	Boot Strap undervoltage lockout (V_BSTx- V_SHx)	Supply rising	3.6	4.2	4.8	V
V_BSTUV	Boot Strap undervoltage lockout (V_BSTx- V_SHx)	Supply falling	3.5	4	4.5	V
V_{BSTUV_HYS}	Bootstrap UV hysteresis	Rising to falling threshold		200		mV
t_BSTUV	Bootstrap undervoltage deglitch time		6	10	22	μs