国产东北女人一级A片,全亚洲日韩精品无码专区精品成人免费一区二区 ,性色AV久久一区二区

ZHCSLS8 August 2020 DRV5825P

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RHB|32
- MPQF130D

散熱焊盤機械數據 (封裝 | 引腳)

RHB|32
- QFND029X

訂購信息

Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
DGND	5	P	Digital ground
DVDD	6	P	3.3-V or 1.8-V digital power supply
VR_DIG	7	P	Internally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices
ADR	8	AI	A table of resistor value (Pull down to GND) will decide device I²C address. See Table 8-5.
GPIO0	9	DI/O	General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and 0x61h). Can be configured to be CMOS output or Open drain output (WARNZ or FAULTZ)
GPIO1	10	DI/O	General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and 0x62h). Can be configured to be CMOS output or Open drain output (WARNZ or FAULTZ)
GPIO2	11	DI/O	General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and 0x63h). Can be configured to be CMOS output or Open drain output (WARNZ or FAULTZ)
LRCLK	12	DI	Word select clock for the digital signal that is active on the serial port's input data line. In I²S, LJ and RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync boundary.
SCLK⁽²⁾	13	DI	Bit clock for the digital signal that is active on the input data line of the serial data port. Sometimes, this pin also be written as "bit clock (BCLK)"
SDIN	14	DI	Data line to the serial data port
SDA	15	DI/O	I²C serial control data interface input/output
SCL	16	DI	I²C serial control clock input
PDN	17	DI	Power down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators.
GVDD	18	P	Gate drive internal regulator output. This pin must not be used to drive external devices
AVDD	19	P	Internally regulated 5-V analog supply voltage. This pin must not be used to drive external devices
AGND	20	P	Analog ground
PVDD	3	P	PVDD voltage input
	4	P
	21	P
	22	P
PGND	25	P	Ground reference for power device circuitry. Connect this pin to system ground.
	26	P
	31	P
	32	P
OUT_B+	23	O	Positive pin for differential speaker amplifier output B
BST_B+	24	P	Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B+
OUT_B-	27	O	Negative pin for differential speaker amplifier output B
BST_B-	28	P	Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B-
BST_A-	29	P	Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A-
OUT_A-	30	O	Negative pin for differential speaker amplifier output A
BST_A+	1	P	Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A+
OUT_A+	2	O	Positive pin for differential speaker amplifier output A
PowerPAD?		P	Connect to the system Ground

(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P = Power, G = Ground (0 V)

(2) Typically written "bit clock (BCLK)" in some audio codecs.