ZHCSLS8 August 2020 DRV5825P
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5 Programming and Control
- 8.6 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
8.3.2 Device Clocking
The DRV5825P device has flexible systems for clocking. Internally, the device requires a number of clocks, mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio Interface.
Figure 8-1 Audio Flow with Respective ClocksFigure 8-1 shows the basic data flow and clock Distribution.
The Serial Audio Interface typically has 3 connection pins which are listed as follows:
- SCLK (Bit Clock)
- LRCLK/FS (Left/Right Word Clock or Frame Sync)
- SDIN (Input Data)
The device has an internal PLL that is used to take SCLK and create the higher rate clocks required by the DSP and the DAC clock.
The DRV5825P device has an audio sampling rate detection circuit that automatically senses which frequency the sampling rate is operating. Common audio sampling frequencies of 32 kHz, 44.1kHz – 48 kHz, 88.2 kHz – 96 kHz are supported. The sampling frequency detector sets the clock for DAC and DSP automatically.
If the input LRCLK/SCLK stopped during music playing, the DRV5825P DSP switches to sleep state and waiting for the clock recovery (Class D output switches to Hiz automatically ), once LRCLK/SCLK recovered, DRV5825P auto recovers to the play mode. There is no need to reload the DSP code.