日韩精品一区二区三区久久久,九色视频免费自拍网站,国产精品久久国产三级国

ZHCSDF3D May 2014 – March 2018 DRV2605L

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

DGS|10
- MPDS035C
YZF|9
- MXBG027N

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

8.5.3.1 General I²C Operation

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. The bus transfers data serially, one bit at a time. The 8-bit address and data bytes are transferred with the most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on the SDA signal indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. Figure 20 shows a typical sequence. The master device generates the 7-bit slave address and the read-write (R/W) bit to start communication with a slave device. The master device then waits for an acknowledge condition. The slave device holds the SDA signal low during the acknowledge clock period to indicate acknowledgment. When this acknowledgment occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All compatible devices share the same signals through a bidirectional bus using a wired-AND connection.

The number of bytes that can be transmitted between start and stop conditions is not limited. When the last word transfers, the master generates a stop condition to release the bus. Figure 20 shows a generic data-transfer sequence.

Use external pullup resistors for the SDA and SCL signals to set the logic-high level for the bus. Pullup resistors with values between 660 Ω and 4.7 kΩ are recommended. Do not allow the SDA and SCL voltages to exceed the DRV2605L supply voltage, V_DD.

NOTE

The DRV2605L slave address is 0x5A (7-bit), or 1011010 in binary.

Figure 20. Typical I²C Sequence

The DRV2605L device operates as an I²C-slave 1.8-V logic thresholds, but can operate up to the V_DD voltage. The device address is 0x5A (7-bit), or 1011010 in binary which is equivalent to 0xB4 (8-bit) for writing and 0xB5 (8-bit) for reading.

封裝選項

機械數據 (封裝 | 引腳)

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

8.5.3.1 General I2C Operation

8.5.3.1 General I²C Operation