ZHCSDF3D May 2014 – March 2018 DRV2605L
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Support for ERM and LRA Actuators
- 8.3.2 Smart-Loop Architecture
- 8.3.3 Open-Loop Operation for LRA
- 8.3.4 Open-Loop Operation for ERM
- 8.3.5 Flexible Front-End Interface
- 8.3.6 Edge Rate Control
- 8.3.7 Constant Vibration Strength
- 8.3.8 Battery Voltage Reporting
- 8.3.9 One-Time Programmable (OTP) Memory for Configuration
- 8.3.10 Low-Power Standby
- 8.3.11 I2C Watchdog Timer
- 8.3.12 Device Protection
- 8.4 Device Functional Modes
- 8.5
Programming
- 8.5.1 Auto-Resonance Engine Programming for the LRA
- 8.5.2 Automatic-Level Calibration Programming
- 8.5.3 I2C Interface
- 8.5.4 Programming for Open-Loop Operation
- 8.5.5 Programming for Closed-Loop Operation
- 8.5.6 Auto Calibration Procedure
- 8.5.7 Programming On-Chip OTP Memory
- 8.5.8 Waveform Playback Programming
- 8.6
Register Map
- 8.6.1 Status (Address: 0x00)
- 8.6.2 Mode (Address: 0x01)
- 8.6.3 Real-Time Playback Input (Address: 0x02)
- 8.6.4 Library Selection (Address: 0x03)
- 8.6.5 Waveform Sequencer (Address: 0x04 to 0x0B)
- 8.6.6 GO (Address: 0x0C)
- 8.6.7 Overdrive Time Offset (Address: 0x0D)
- 8.6.8 Sustain Time Offset, Positive (Address: 0x0E)
- 8.6.9 Sustain Time Offset, Negative (Address: 0x0F)
- 8.6.10 Brake Time Offset (Address: 0x10)
- 8.6.11 Audio-to-Vibe Control (Address: 0x11)
- 8.6.12 Audio-to-Vibe Minimum Input Level (Address: 0x12)
- 8.6.13 Audio-to-Vibe Maximum Input Level (Address: 0x13)
- 8.6.14 Audio-to-Vibe Minimum Output Drive (Address: 0x14)
- 8.6.15 Audio-to-Vibe Maximum Output Drive (Address: 0x15)
- 8.6.16 Rated Voltage (Address: 0x16)
- 8.6.17 Overdrive Clamp Voltage (Address: 0x17)
- 8.6.18 Auto-Calibration Compensation Result (Address: 0x18)
- 8.6.19 Auto-Calibration Back-EMF Result (Address: 0x19)
- 8.6.20 Feedback Control (Address: 0x1A)
- 8.6.21 Control1 (Address: 0x1B)
- 8.6.22 Control2 (Address: 0x1C)
- 8.6.23 Control3 (Address: 0x1D)
- 8.6.24 Control4 (Address: 0x1E)
- 8.6.25 Control5 (Address: 0x1F)
- 8.6.26 LRA Open Loop Period (Address: 0x20)
- 8.6.27 V(BAT) Voltage Monitor (Address: 0x21)
- 8.6.28 LRA Resonance Period (Address: 0x22)
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
8.3.5.6.2 Edge Trigger
A low-to-high transition on the IN/TRIG pin sets the GO bit. The playback sequence indicated in the waveform sequencer plays as normal. The user can cancel the transaction by clearing the GO bit. An additional low-to-high transition while the GO bit is high also cancels the transaction which clears and resets the GO bit. Clearing the trigger pin (high-to-low transition) does nothing, therefore the user can send a short pulse without knowing how long the waveform is. The pulse width should be at least 1 µs to ensure detection.
Figure 14. Edge Trigger Mode