ZHCSLL4 December 2021 DP83TC814R-Q1 , DP83TC814S-Q1
PRODUCTION DATA
For these typical applications, use the following as design parameters from the table below. Refer to Power Supply Recommendations section for detailed connection diagram.
| DESIGN PARAMETER | EXAMPLE VALUE |
|---|---|
| VDDIO | 1.8 V, 2.5 V, or 3.3 V |
| VDDMAC | 1.8 V, 2.5 V, or 3.3 V |
| VDDA | 3.3 V |
| Decoupling capacitors VDDIO(2)(3) | 0.01 μF |
| (Optional) ferrite bead for VDDIO(3) | 1 kΩ at 100 MHz (BLM18KG601SH1D) |
| Decoupling capacitors VDDMAC(2) | 0.01 μF, 0.47 μF |
| Ferrite bead for VDDMAC | 1 kΩ at 100 MHz (BLM18KG601SH1D) |
| Decoupling capacitors VDDA (2) | 0.01 μF, 0.47 μF |
| (Optional) ferrite bead for VDDA | 1 kΩ at 100 MHz (BLM18KG601SH1D) |
| Decoupling capacitors VDDA(pin 7) |
0.1 μF |
| DC Blocking Capacitors (2) | 0.1 μF |
| Common-Mode Choke | 200 μH |
| Common Mode Termination Resistors(1) | 1 kΩ |
| MDI Coupling Capacitor (2) | 4.7 nF |
| ESD Shunt(2) | 100 kΩ |
| Reference Clock | 25 MHz |