ZHCSLL4 December 2021 DP83TC814R-Q1 , DP83TC814S-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|---|---|
| MII TIMING | ||||||
| T1.1 | TX_CLK High / Low Time | 16 | 20 | 24 | ns | |
| T1.2 | TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK | 10 | ns | |||
| T1.3 | TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK | 0 | ns | |||
| T2.1 | RX_CLK High / Low Time | 16 | 20 | 24 | ns | |
| T2.2 | RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising | 10 | 30 | ns | ||
| RMII MASTER TIMING | ||||||
| T3.1 | RMII Master Clock Period | 20 | ns | |||
| RMII Master Clock Duty Cycle | 35 | 65 | % | |||
| T3.2 | TX_D[1:0], TX_ER, TX_EN Setup to RMII Master Clock | 4 | ns | |||
| T3.3 | TX_D[1:0], TX_ER, TX_EN Hold from RMII Master Clock | 2 | ns | |||
| T3.4 | RX_D[1:0], RX_ER, CRS_DV Delay from RMII Master Clock rising edge | 4 | 10 | 14 | ns | |
| RMII SLAVE TIMING | ||||||
| T3.1 | Input Reference Clock Period | 20 | ns | |||
| Reference Clock Duty Cycle | 35 | 65 | % | |||
| T3.2 | TX_D[1:0], TX_ER, TX_EN Setup to XI Clock rising | 4 | ns | |||
| T3.3 | TX_D[1:0], TX_ER, TX_EN Hold from XI Clock rising | 2 | ns | |||
| T3.4 | RX_D[1:0], RX_ER, CRS_DV Delay from XI Clock rising | 4 | 14 | ns | ||
| RGMII INPUT TIMING | ||||||
| Tcyc | Clock Cycle Duration | TX_CLK | 36 | 40 | 44 | ns |
| Tsetup(align) | TX_D[3:0], TX_CTRL Setup to TX_CLK (Align Mode) | 1 | 2 | ns | ||
| Thold(align) | TX_D[3:0], TX_CTRL Hold from TX_CLK (Align Mode) | 1 | 2 | ns | ||
| RGMII OUTPUT TIMING | ||||||
| Tskew(align) | RX_D[3:0], RX_CTRL Delay from RX_CLK (Align Mode Enabled) | On PHY Pins | -750 | 750 | ps | |
| Tsetup(shift) | RX_D[3:0], RX_CTRL Delay from RX_CLK (Shift Mode Enabled, default) |
On PHY Pins | 2 | ns | ||
| Tcyc | Clock Cycle Duration | RX_CLK | 36 | 40 | 44 | ns |
| Duty_G | Duty Cycle | RX_CLK | 45 | 50 | 55 | % |
| Tr/Tf | Rise / Fall Time ( 20% to 80%) | CLOAD = 5pF | 1.2 | ns | ||
| SMI TIMING | ||||||
| T4.1 | MDC to MDIO (Output) Delay Time | 25pF load capacitance | 0 | 40 | ns | |
| T4.2 | MDIO (Input) to MDC Setup Time | 10 | ns | |||
| T4.3 | MDIO (Input) to MDC Hold Time | 10 | ns | |||
| MDC Frequency | 2.5 | 20 | MHz | |||
| POWER-UP TIMING | ||||||
| T5.1 | Supply ramp time: For all supplies (1) | 0.2 | 8 | ms | ||
| T5.2 | Supply ramp delay offset: For all supplies | 10 | ms | |||
| T5.3 | XTAL Startup / Settling: Powerup to XI good/stabilized | 0.35 | ms | |||
| T5.4 | Oscillator stabilization time from power up | 10 | ms | |||
| Last Supply power up To Reset Release | 10 | ms | ||||
| T5.5 | Post power-up to SMI ready: Post Power-up wait time required before MDC preamble can be sent for register access | 10 | ms | |||
| T5.6 | Power-up to Strap latch-in | 10 | ms | |||
| T5.7 | CLKOUT Startup/Settling: Powerup to CLKOUT good/stabilized | 10 | ms | |||
| T5.8 | Power-up to idle stream | 10 | ms | |||
| RESET TIMING (RESET_N) | ||||||
| T6.1 | Reset Pulse Width: Miminum Reset pulse width to be able to reset | 720 | ns | |||
| T6.2 | Reset to SMI ready: Post reset wait time required before MDC preamble can be sent for register access | 1 | ms | |||
| T6.3 | Reset to Strap latch-in: Hardware configuration pins transition to output drivers | 40 | μs | |||
| T6.4 | Reset to idle stream | 1800 | μs | |||
| TRANSMIT LATENCY TIMING | ||||||
| MII Rising edge TX_CLK with assertion TX_EN to SSD symbol on MD | 205 | 233 | ns | |||
| Slave RMII Rising edge XI clock with assertion TX_EN to SSD symbol on MDI | 374 | 409 | ns | |||
| Master RMII Rising edge clock with assertion TX_EN to SSD symbol on MDI | 382 | 408 | ns | |||
| RGMII Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI | 370 | 390 | ns | |||
| First symbol of SGMII to SSD symbol on MDI | 420 | 456 | ns | |||
| RECEIVE LATENCY TIMING | ||||||
| SSD symbol on MDI to MII Rising edge of RX_CLK with assertion of RX_DV | 467 | 491 | ns | |||
| SSD symbol on MDI to Slave RMII Rising edge of XI clock with assertion of CRS_DV | 527 | 574 | ns | |||
| SSD symbol on MDI to Master RMII Rising edge of Master clock with assertion of CRS_DV | 521 | 557 | ns | |||
| SSD symbol on MDI to Rising edge of RGMII RX_CLK with assertion of RX_CTRL | 484 | 511 | ns | |||
| SSD symbol on MDI to first symbol of SGMII | 708 | 788 | ns | |||
| 25 MHz OSCILLATOR REQUIREMENTS | ||||||
| Frequency Tolerance | -100 | +100 | ppm | |||
| Rise / Fall Time (10%-90%) | 8 | ns | ||||
| Jitter Tolerance (RMS) | 25 | ps | ||||
| XI Duty Cycle in external clock mode | 40 | 60 | % | |||
| 50 MHz OSCILLATOR REQUIREMENTS | ||||||
| Frequency | 50 | MHz | ||||
| Frequency Tolerance and Stability Over temperature and aging | –100 | 100 | ppm | |||
| Rise / Fall Time (10% - 90%) | 4 | ns | ||||
| Duty Cycle | 35 | 65 | % | |||
| 25 MHz CRYSTAL REQUIREMENTS | ||||||
| Frequency | 25 | MHz | ||||
| Frequency Tolerance and Stability Over temperature and aging | –100 | 100 | ppm | |||
| Equivalent Series Resistance | 100 | Ω | ||||
| OUTPUT CLOCK TIMING (25 MHz) | ||||||
| Frequency (PPM) | -100 | 100 | - | |||
| Duty Cycle | 40 | 60 | % | |||
| Rise Time | 5000 | ps | ||||
| Fall Time | 5000 | ps | ||||
| Jitter (Short Term) | 1000 | ps | ||||
| Frequency | 25 | MHz | ||||