ZHCSEC3F October 2015 – January 2025 DP83867CS , DP83867E , DP83867IS
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
| BIT | BIT NAME | DEFAULT | DESCRIPTION |
|---|---|---|---|
| 15:8 | RESERVED | 0x04 | RESERVED |
| 7:5 | TM_CH_SEL | 0x0 | Test mode Channel Select. |
| If bit 7 is set then Test mode is driven on all 4 channels. If bit 7 is cleared then test modes are driven according to bits 6:5 as follows: | |||
| 00: Channel A | |||
| 01: Channel B | |||
| 10: Channel C | |||
| 11: Channel D | |||
| 4:0 | RESERVED | 0x00 | RESERVED |