ZHCSFD6G july 2016 – august 2023 DP83822H , DP83822HF , DP83822I , DP83822IF
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 Timing Requirements, Power-Up Timing
- 7.7 Timing Requirements, Power-Up With Unstable XI Clock
- 7.8 Timing Requirements, Reset Timing
- 7.9 Timing Requirements, Serial Management Timing
- 7.10 Timing Requirements, 100 Mbps MII Transmit Timing
- 7.11 Timing Requirements, 100 Mbps MII Receive Timing
- 7.12 Timing Requirements, 10 Mbps MII Transmit Timing
- 7.13 Timing Requirements, 10 Mbps MII Receive Timing
- 7.14 Timing Requirements, RMII Transmit Timing
- 7.15 Timing Requirements, RMII Receive Timing
- 7.16 Timing Requirements, RGMII
- 7.17 Normal Link Pulse Timing
- 7.18 Auto-Negotiation Fast Link Pulse (FLP) Timing
- 7.19 10BASE-Te Jabber Timing
- 7.20 100BASE-TX Transmit Latency Timing
- 7.21 100BASE-TX Receive Latency Timing
- 7.22 Timing Diagrams
- 7.23 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4
Device Functional Modes
- 8.4.1 MAC Interfaces
- 8.4.2
Serial Management Interface
- 8.4.2.1 Extended Register Space Access
- 8.4.2.2 Write Address Operation
- 8.4.2.3 Read Address Operation
- 8.4.2.4 Write (No Post Increment) Operation
- 8.4.2.5 Read (No Post Increment) Operation
- 8.4.2.6 Write (Post Increment) Operation
- 8.4.2.7 Read (Post Increment) Operation
- 8.4.2.8 Example Write Operation (No Post Increment)
- 8.4.2.9 Example Read Operation (No Post Increment)
- 8.4.3 100BASE-TX
- 8.4.4 100BASE-FX
- 8.4.5 10BASE-Te
- 8.4.6 Auto-Negotiation (Speed / Duplex Selection)
- 8.4.7 Auto-MDIX Resolution
- 8.4.8 Loopback Modes
- 8.4.9 BIST Configurations
- 8.4.10 Cable Diagnostics
- 8.4.11 Fast Link Down Functionality
- 8.5 Programming
- 8.6 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.5.1 Hardware Bootstrap Configurations
The DP83822 uses the receive path functional pins as bootstrap options to place the device into specific modes of operation. The values of these pins are sampled at power up or hardware reset, through either the RESET pin or bit[15] in the PHY Reset Control Register (PHYRCR, address 0x001F).
The DP83822 bootstrap pins are 4-level, which are described in greater detail below.
Because bootstrap pins may have alternate functions after reset is de-asserted, they should not be connected directly to VCC or GND. pullup and pulldown resistors are required for proper operation.
Pins: COL, LED_0, CRS and RX_ER have internal pullup resistors. All other pins with bootstraps have internal pulldown resistors. To account for the difference between the internal pullup and pulldown, please reference Table 8-8 and Table 8-9 below for proper implementation.
LED_0 and LED_1 require parallel pullup or pulldown resistors when using the pin in conjunction with an LED and current limiting resistor.
Configuration of the device may be done via 4-level strapping or via serial management interface. A pullup resistor and a pulldown resistor of suggested values should be used to set the voltage ratio of the bootstrap pin input and the supply to select one of the possible modes.
Figure 8-10 Bootstrap Circuits| MODE | IDEAL RH (k?) | IDEAL RL (k?) |
|---|---|---|
| PULLDOWN PINS (9 kΩ) | ||
| 1 (Default) | OPEN | OPEN |
| 2 | 10 | 2.49 |
| 3 | 5.76 | 2.49 |
| 4 | 2.49 | OPEN |
| PULLUP PINS (50 kΩ) | ||
| 1 | OPEN | 1.96 |
| 2 | 13 | 1.96 |
| 3 | 6.2 | 1.96 |
| 4 (Default) | OPEN | OPEN |
| TARGET VOLTAGE | MODE 1 | MODE 2 | MODE 3 | MODE 4 |
|---|---|---|---|---|
| Vmax (V) | 0.098 x VDDIO | 0.181 x VDDIO | 0.277 x VDDIO | VDDIO |
| Vtyp (V) | 0 | 0.165 x VDDIO | 0.252 x VDDIO | VDDIO |
| Vmin (V) | 0 | 0.148 x VDDIO | 0.227 x VDDIO | 0.694 x VDDIO |
Table 8-10 describes the DP83822 configuration bootstraps:
| PIN NAME | PIN # | DEFAULT | STRAP FUNCTION | DESCRIPTION | ||
|---|---|---|---|---|---|---|
| COL | 29 | [01] | MODE | FX_EN | PHY_AD0 | FX_EN: Enables 100BASE-FX when set to ‘1’ PHY_AD0: PHY Address bit[0] |
| 1 | 0 | 0 | ||||
| 2 | 1 | 0 | ||||
| 3 | 1 | 1 | ||||
| 4 (Default) | 0 | 1 | ||||
| RX_D0 | 30 | [10] | MODE | AN_1 | PHY_AD1 | AN_1: See Table 8-11 below PHY_AD1: PHY Address bit[1] |
| 1 (Default) | 1 | 0 | ||||
| 2 | 0 | 0 | ||||
| 3 | 0 | 1 | ||||
| 4 | 1 | 1 | ||||
| RX_D1 | 31 | [00] | MODE | EEE_EN | PHY_AD2 | EEE_EN: Enables EEE operation when set to '1' PHY_AD2: PHY Address bit [2] |
| 1 (Default) | 0 | 0 | ||||
| 2 | 1 | 0 | ||||
| 3 | 1 | 1 | ||||
| 4 | 0 | 1 | ||||
| RX_D2 | 32 | [00] | MODE | FLD_EN | PHY_AD3 | FLD_EN: Enables Fast Link Drop when set to '1'. Energy Detection, Low SNR threshold and RX_ER will be enabled. PHY_AD3: PHY Address bit[3] |
| 1 (Default) | 0 | 0 | ||||
| 2 | 1 | 0 | ||||
| 3 | 1 | 1 | ||||
| 4 | 0 | 1 | ||||
| RX_D3 | 1 | [10] | MODE | AN_EN | PHY_AD4 | AN_EN: See Table 8-11 below PHY_AD4: PHY Address bit[4] |
| 1 (Default) | 1 | 0 | ||||
| 2 | 0 | 0 | ||||
| 3 | 0 | 1 | ||||
| 4 | 1 | 1 | ||||
| LED_0 | 17 | [X1] | MODE | RESERVED | AN_0 | AN_0:
See Table 8-11 below |
| 1 | X | 0 | ||||
| 2 | X | Do Not Use(1) | ||||
| 3 | X | Do Not Use(1) | ||||
| 4 (Default) | X | 1 | ||||
| LED_1 | 24 | [1X] | Mode | RESERVED | No added functionality. Do not use Mode 2 & 3 |
|
| 1 (Default) | 0 | |||||
| 2 | Do Not Use(1) | |||||
| 3 | Do Not Use(1) | |||||
| 4 | 1 | |||||
| CRS | 27 | [01] | MODE | LED_SPEED | LED_CFG | LED_CFG:
See below LED_SPEED: See Table 8-12 below |
| 1 | 0 | 0 | ||||
| 2 | 1 | 0 | ||||
| 3 | 1 | 1 | ||||
| 4 (Default) | 0 | 1 | ||||
| RX_ER | 28 | [01] | MODE | RGMII_EN | AMDIX_EN (SD_EN) |
AMDIX_EN: Enables Auto-MDIX when set to '1' RGMII_EN: See Table 8-13 below SD_EN: Enables 100BASE-FX Signal Detection on LED_1 when set to '1'. FX_EN strap must be enabled for SD_EN strap to be functional. Signal Detection is Active HIGH, but polarity can be changed using the Fiber General Configuration Register (FIBER GENCFG, address 0x0465). |
| 1 | 0 | 0 | ||||
| 2 | 1 | 0 | ||||
| 3 | 1 | 1 | ||||
| 4 (Default) | 0 | 1 | ||||
| RX_DV | 26 | [00] | MODE | XI_50 | RMII_EN | XI_50: See Table 8-13 below RMII_EN: See Table 8-13 below |
| 1 (Default) | 0 | 0 | ||||
| 2 | 1 | 0 | ||||
| 3 | 0 | 1 | ||||
| 4 | 1 | 1 | ||||
| FX_EN | AN_EN | AN_1 | AN_0 | Description |
|---|---|---|---|---|
| Force Modes | ||||
| 0 | 0 | 0 | 0 | 10BASE-Te, Half-Duplex |
| 0 | 0 | 0 | 1 | 10BASE-Te, Full-Duplex |
| 0 | 0 | 1 | 0 | 100BASE-TX, Half-Duplex |
| 0 | 0 | 1 | 1 | 100BASE-TX, Full-Duplex |
| Advertised Modes | ||||
| 0 | 1 | 0 | 0 | 10BASE-Te, Half-Duplex |
| 0 | 1 | 0 | 1 | 10BASE-Te, Half/Full-Duplex |
| 0 | 1 | 1 | 0 | 10BASE-Te, Half-Duplex 100BASE-TX, Half-Duplex |
| 0 | 1 | 1 | 1 | 10BASE-Te, Half/Full-Duplex 100BASE-TX, Half/Full-Duplex |
| Fiber Modes | ||||
| 1 | X | X | 0 | 100BASE-FX, Half Duplex |
| 1 | X | X | 1 | 100BASE-FX, Full Duplex |
| CRS Strap Mode | LED_SPEED | LED_CFG[0] | LED_0 | LED_1 |
|---|---|---|---|---|
| 1 | 0 | 0 | ON for Good Link BLINK for TX/RX Activity |
LED_1 in Tri-State |
| 2 | 1 | 0 | ON for Good Link BLINK for TX/RX Activity |
ON for 100 Mbps SPEED OFF for 10 Mbps SPEED |
| 3 | 1 | 1 | ON for Good Link OFF for No Link |
ON for 100 Mbps SPEED OFF for 10 Mbps SPEED |
| 4 | 0 | 1 | ON for Good Link OFF for No Link |
LED_1 in Tri-State |
| RGMII_EN | RMII_EN | XI_50 | Description |
|---|---|---|---|
| 0 | 0 | 0 | MII, 25-MHz Reference Clock |
| 0 | 0 | 1 | Reserved |
| 0 | 1 | 0 | RMII, 25-MHz Reference Clock |
| 0 | 1 | 1 | RMII, 50-MHz Reference Clock |
| 1 | X | 0 | RGMII, 25-MHz Reference Clock |
| 1 | X | 1 | Reserved |