ZHCSFD6G july 2016 – august 2023 DP83822H , DP83822HF , DP83822I , DP83822IF
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 Timing Requirements, Power-Up Timing
- 7.7 Timing Requirements, Power-Up With Unstable XI Clock
- 7.8 Timing Requirements, Reset Timing
- 7.9 Timing Requirements, Serial Management Timing
- 7.10 Timing Requirements, 100 Mbps MII Transmit Timing
- 7.11 Timing Requirements, 100 Mbps MII Receive Timing
- 7.12 Timing Requirements, 10 Mbps MII Transmit Timing
- 7.13 Timing Requirements, 10 Mbps MII Receive Timing
- 7.14 Timing Requirements, RMII Transmit Timing
- 7.15 Timing Requirements, RMII Receive Timing
- 7.16 Timing Requirements, RGMII
- 7.17 Normal Link Pulse Timing
- 7.18 Auto-Negotiation Fast Link Pulse (FLP) Timing
- 7.19 10BASE-Te Jabber Timing
- 7.20 100BASE-TX Transmit Latency Timing
- 7.21 100BASE-TX Receive Latency Timing
- 7.22 Timing Diagrams
- 7.23 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4
Device Functional Modes
- 8.4.1 MAC Interfaces
- 8.4.2
Serial Management Interface
- 8.4.2.1 Extended Register Space Access
- 8.4.2.2 Write Address Operation
- 8.4.2.3 Read Address Operation
- 8.4.2.4 Write (No Post Increment) Operation
- 8.4.2.5 Read (No Post Increment) Operation
- 8.4.2.6 Write (Post Increment) Operation
- 8.4.2.7 Read (Post Increment) Operation
- 8.4.2.8 Example Write Operation (No Post Increment)
- 8.4.2.9 Example Read Operation (No Post Increment)
- 8.4.3 100BASE-TX
- 8.4.4 100BASE-FX
- 8.4.5 10BASE-Te
- 8.4.6 Auto-Negotiation (Speed / Duplex Selection)
- 8.4.7 Auto-MDIX Resolution
- 8.4.8 Loopback Modes
- 8.4.9 BIST Configurations
- 8.4.10 Cable Diagnostics
- 8.4.11 Fast Link Down Functionality
- 8.5 Programming
- 8.6 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
9.2.2.1.1.2 Crystal
The use of a 25-MHz, parallel, 20-pF load crystal is recommended if operating with a crystal. A typical connection diagram is shown below for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads.
Figure 9-4 Crystal Oscillator CircuitTable 9-1 25-MHz Oscillator Specification
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| Frequency | 25 | MHz | |||
| Frequency Tolerance | Including operational temperature, aging and other factors | -100 | 100 | ppm | |
| Rise / Fall Time | 10% - 90% | 8 | nsec | ||
| Jitter (Short Term) | Cycle-to-cycle | 50 | 100 | psec | |
| Jitter (Long Term) | Accumulative over 10 ms | 1 | nsec | ||
| Symmetry | Duty Cycle | 40 | 60 | % | |
| Load Capacitance | 15 | 30 | pF |
Table 9-2 50-MHz Oscillator Specification
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| Frequency | 50 | MHz | |||
| Frequency Tolerance | Including operational temperature, aging and other factors | -100 | 100 | ppm | |
| Rise / Fall Time | 10% - 90% | 8 | nsec | ||
| Jitter (Short Term) | Cycle-to-cycle | 50 | psec | ||
| Jitter (Long Term) | Accumulative over 10 ms | 1 | nsec | ||
| Symmetry | Duty Cycle | 40 | 60 | % | |
| Load Capacitance | 15 | 30 | pF |
Table 9-3 25-MHz Crystal Specification
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| Frequency | 25 | MHz | |||
| Frequency Tolerance | Including operational temperature, aging and other factors | -100 | 100 | ppm | |
| Load Capacitance | 10 | 40 | pF |