ZHCSFD6G july 2016 – august 2023 DP83822H , DP83822HF , DP83822I , DP83822IF
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 Timing Requirements, Power-Up Timing
- 7.7 Timing Requirements, Power-Up With Unstable XI Clock
- 7.8 Timing Requirements, Reset Timing
- 7.9 Timing Requirements, Serial Management Timing
- 7.10 Timing Requirements, 100 Mbps MII Transmit Timing
- 7.11 Timing Requirements, 100 Mbps MII Receive Timing
- 7.12 Timing Requirements, 10 Mbps MII Transmit Timing
- 7.13 Timing Requirements, 10 Mbps MII Receive Timing
- 7.14 Timing Requirements, RMII Transmit Timing
- 7.15 Timing Requirements, RMII Receive Timing
- 7.16 Timing Requirements, RGMII
- 7.17 Normal Link Pulse Timing
- 7.18 Auto-Negotiation Fast Link Pulse (FLP) Timing
- 7.19 10BASE-Te Jabber Timing
- 7.20 100BASE-TX Transmit Latency Timing
- 7.21 100BASE-TX Receive Latency Timing
- 7.22 Timing Diagrams
- 7.23 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4
Device Functional Modes
- 8.4.1 MAC Interfaces
- 8.4.2
Serial Management Interface
- 8.4.2.1 Extended Register Space Access
- 8.4.2.2 Write Address Operation
- 8.4.2.3 Read Address Operation
- 8.4.2.4 Write (No Post Increment) Operation
- 8.4.2.5 Read (No Post Increment) Operation
- 8.4.2.6 Write (Post Increment) Operation
- 8.4.2.7 Read (Post Increment) Operation
- 8.4.2.8 Example Write Operation (No Post Increment)
- 8.4.2.9 Example Read Operation (No Post Increment)
- 8.4.3 100BASE-TX
- 8.4.4 100BASE-FX
- 8.4.5 10BASE-Te
- 8.4.6 Auto-Negotiation (Speed / Duplex Selection)
- 8.4.7 Auto-MDIX Resolution
- 8.4.8 Loopback Modes
- 8.4.9 BIST Configurations
- 8.4.10 Cable Diagnostics
- 8.4.11 Fast Link Down Functionality
- 8.5 Programming
- 8.6 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
8.3.3 Start of Frame Detect for IEEE 1588 Time Stamp
The DP83822 supports an IEEE 1588 indication pulse at the SFD (start frame delimiter) for receive and transmit paths. The pulse can be delivered to any of the following pins: LED_0, LED_1 (GPIO1), COL (GPIO2), RX_D3 (GPIO3), INT/PWDN_N and CRS. The 1588 Time Stamp pulse indicates the actual time the symbol is presented on the lines (for transmit), or the first symbol received (for receive). The exact timing of the pulse can be adjusted via the IEEE 1588 PTP Configuration Register (PTPCFG, address 0x003F). Each increment of phase value is an 8-ns step.
Figure 8-3 IEEE 1588 Message Timestamp PointThere are three registers that are able to control the routing of the IEEE 1588 transmit and receive indications. The IEEE 1588 PTP Pin Select Register (PTPPSEL, address 0x003E) is able to route both transmit and receive indications to LED_0 (GPIO1), COL (GPIO2), CRS and INT/PWDN_N, which is also found in the TLK105L and TLK106L PHYs. Two additional registers in the DP83822 allow for additional pin selections and a centralized location for GPIO controls through the use of the IO MUX GPIO Control Register #1 and #2 (IOCTRL1 and IOCTRL2, address 0x0462 and address 0x0463). After enabling/setting the RX_SFD and TX_SFD pins in register IOCTRLx, please write the following two registers:
- Program (Register 0x0456 = value 0x000A)
- Program (Register 0x04A0 = value
0x1080)
- Please note register 0x04A0 is enabling "bit 7: WOL". This helps improve the accuracy of SFD detection and is not a must change. This will not cause PHY to detect WoL packets, as WoL function needs additional register configurations.
Note: A software reset has to be performed to load these register values (Register 0x001F = value 0x4000)