ZHCSNO0B April 2021 – November 2021 DP83561-SP
PRODUCTION DATA
| PARAMETER | MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|---|
| POWER-UP TIMING (2, 3 supply mode) | |||||
| Supply ramp rate: For all supplies | 0.5 | 100 | ms | ||
| Supply delay offset between fully ramped (2V5, 1V1) and (VDDIO, 1V8) (3) | 0 | 50 | ms | ||
| T1 | Last Supply power rail ramp to RESET_N | 200 | ms | ||
| T2 | Powerup to SMI ready: Post power-up stabilization time prior to MDC preamble for register access | 200 | ms | ||
| T3 | Powerup to Strap latchin: Hardware configuration pins transition to output drivers | 200 | ms | ||
| Powerup to FLP | 2000 | ms | |||
| RESET TIMING | |||||
| T1 | Reset to SMI ready: Post reset stabilization time prior to MDC preamble for register access | 30 | us | ||
| T3 | RESET PULSE Width: Miminum Reset pulse width to be able to reset | 720 | ns | ||
| T4 | Reset to FLP | 1750 | ms | ||
| T4 | Reset to 100M signaling (strapped mode) | 194 | us | ||
| T4 | Reset to MAC clock | 195 | us | ||
| COPPER LINK TIMING | |||||
| T1 | Loss of Idles to Link LED low in Fast link down mode (100M) | 10 | us | ||
| Loss of Idles to Link LED low in Fast link down mode (1000M) | 10 | us | |||
| MII 100M TIMING | |||||
| T1 | TX_CLK High / Low Time | 16 | 20 | 24 | ns |
| T2 | TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK | 10 | ns | ||
| T3 | TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK | 0 | ns | ||
| T1 | RX_CLK High / Low Time | 16 | 20 | 24 | ns |
| T2 | RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising | 10 | 30 | ns | |
| MII 10M Timings | |||||
| 10M | TX_CLK High / Low Time | 190 | 200 | 210 | ns |
| TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK | 25 | ns | |||
| TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK | 0 | ns | |||
| RX_CLK High / Low Time | 160 | 200 | 240 | ns | |
| RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising | 100 | 300 | ns | ||
| RGMII OUTPUT TIMING (1G) | |||||
| TskewT | Data to Clock Output Skew (Non-Delay Mode)(2) | -600 | 625 | ps | |
| TskewT(Delay) | Data to Clock Output Skew (Delay Mode : 2 ns default) | 1.5 | 2 | 2.5 | ns |
| TsetupT | Data to Clock Output Setup ( Delay Mode) | 1.2 | ns | ||
| TholdT | Data to Clock Output Hold ( Delay Mode) | 1.2 | ns | ||
| Tcyc | Clock Cycle Duration | 7.2 | 8 | 8.8 | ns |
| Duty Cycle | 45 | 50 | 58 | % | |
| Rise / Fall Time ( 20% to 80%) : with 5 pF Capacitive load | 0.85 | ns | |||
| RGMII INPUT TIMING (1G) | |||||
| TsetupR | TX data to clock input setup | 1 | ns | ||
| TholdR | TX clock to data input hold | 1 | ns | ||
| DLL delay TX Input step | 250 | ps | |||
| SMI TIMING | |||||
| T1 | MDC to MDIO (Output) Delay Time (25 pF Load) | 0 | 20 | ns | |
| T2 | MDIO (Input) to MDC Setup Time | 10 | ns | ||
| T3 | MDIO (Input) to MDC Hold Time | 10 | ns | ||
| T4 | MDC Frequency (25 pF Load) | 2.5 | 24 | MHz | |
| OUTPUT CLOCK TIMING (25MHz clockout) | |||||
| Frequency (PPM) | -100 | 100 | - | ||
| Duty Cycle | 40 | 60 | % | ||
| Rise Time (5 pF Load) | 5000 | ps | |||
| Fall Time (5 pF Load) | 5000 | ps | |||
| Jitter (RMS) | 40 | ps | |||
| Jitter (Long Term) | 375 | ps | |||
| 25MHz INPUT CLOCK tolerance | |||||
| Frequency Tolerance | -100 | +100 | ppm | ||
| Rise / Fall Time (10%-90%) | 8 | ns | |||
| Jitter Tolerance (Accumulated) | 75 | ps | |||
| Duty Cycle | 40 | 60 | % | ||
| TRANSMIT LATENCY TIMING | |||||
| Copper | RGMII to Cu (10M) : Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI | 2560 | ns | ||
| Copper | MII to Cu (10M): Rising edge TX_CLK with assertion TX_EN to SSD symbol on MDI | 525 | ns | ||
| Copper | RGMII to Cu (100M): Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI | 169 | ns | ||
| Copper | MII to Cu (100M): Rising edge TX_CLK with assertion TX_EN to SSD symbol on MDI | 64 | ns | ||
| Copper | RGMII to Cu (1G): Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI | 106 | ns | ||
| RECEIVE LATENCY TIMING | |||||
| Copper | Cu to RGMII (10M): SSD symbol on MDI to Rising edge of RX_CLK with assertion of RX_CTRL | 3000 | ns | ||
| Copper | Cu to MII (10M): SSD symbol on MDI to Rising edge of RX_CLK with assertion of RX_DV | 1650 | ns | ||
| Copper | Cu to RGMII (100M): SSD symbol on MDI to a) Rising edge of RX_DV with assertion of RX_CTRL b) Rising edge of RX_DV with assertion of RX_Dx | 192 | ns | ||
| Copper | Cu to MII (100M): SSD symbol on MDI to a) Rising edge of RX_DV with assertion of RX_CTRL b) Rising edge of RX_DV with assertion of RX_Dx | 220 | ns | ||
| Copper | Cu to RGMII (1G): SSD symbol on MDI to a) Rising edge of RX_DV with assertion of RX_CTRL b) Rising edge of RX_DV with assertion of RX_Dx | 278 | ns | ||