ZHCSNO0B April 2021 – November 2021 DP83561-SP
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Copper Ethernet
- 7.3.2 MAC Interfaces
- 7.3.3
Auto-Negotiation
- 7.3.3.1 Speed and Duplex Selection - Priority Resolution
- 7.3.3.2 Master and Slave Resolution
- 7.3.3.3 Pause and Asymmetrical Pause Resolution
- 7.3.3.4 Next Page Support
- 7.3.3.5 Parallel Detection
- 7.3.3.6 Restart Auto-Negotiation
- 7.3.3.7 Enabling Auto-Negotiation Through Software
- 7.3.3.8 Auto-Negotiation Complete Time
- 7.3.3.9 Auto-MDIX Resolution
- 7.3.4 Speed Optimization
- 7.3.5 Radiation Performance
- 7.3.6 WoL (Wake-on-LAN) Packet Detection
- 7.3.7 Start of Frame Detect for IEEE 1588 Time Stamp
- 7.3.8 Cable Diagnostics
- 7.3.9 Clock Output
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1
Serial Management Interface
- 7.5.1.1
Extended Address Space Access
- 7.5.1.1.1 Write Address Operation
- 7.5.1.1.2 Read Address Operation
- 7.5.1.1.3 Write (No Post Increment) Operation
- 7.5.1.1.4 Read (No Post Increment) Operation
- 7.5.1.1.5 Write (Post Increment) Operation
- 7.5.1.1.6 Read (Post Increment) Operation
- 7.5.1.1.7 Example of Read Operation Using Indirect Register Access
- 7.5.1.1.8 Example of Write Operation Using Indirect Register Access
- 7.5.1.1
Extended Address Space Access
- 7.5.2 Interrupt
- 7.5.3 BIST Configuration
- 7.5.4 Strap Configuration
- 7.5.5 LED Configuration
- 7.5.6 LED Operation From 1.8-V I/O VDD Supply
- 7.5.7 Reset Operation
- 7.5.1
Serial Management Interface
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.5.1 Serial Management Interface
The Serial Management Interface (SMI), provides access to the DP83561-SP internal register space for status information and configuration. The SMI is compatible with IEEE 802.3-2002 clause 22. The implemented register set consists of the registers required by the IEEE 802.3, plus several others to provide additional visibility and controllability of the DP83561-SP device.
The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock is sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of 24 MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when the bus is idle.
The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched on the rising edge of the MDC clock. The MDIO pin requires a pullup resistor (2.2 kΩ) which, during IDLE and turnaround, pulls MDIO high.
Up to 16 PHYs can share a common SMI bus. To distinguish between the PHYs, a 4-bit address is used. During power-up reset, the DP83561-SP latches the PHY_ADD configuration pins to determine its address.
The management entity must not start an SMI transaction in the first cycle after power-up reset. To maintain valid operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is deasserted. In normal MDIO transactions, the register address is taken directly from the management-frame reg_addr field, thus allowing direct access to 32 16-bit registers (including those defined in IEEE 802.3 and vendor specific). The data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern makes sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device may actively drive the MDIO signal during the first bit of turnaround. The addressed DP83561-SP drives the MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 7-12 shows the timing relationship between MDC and the MDIO as driven and received by the Station (STA) and the DP83561-SP (PHY) for a typical register read access.
For write transactions, the station-management entity writes data to the addressed DP83561-SP, thus eliminating the requirement for MDIO turnaround. The turnaround time is filled by the management entity by inserting <10>. Figure 7-13 shows the timing relationship for a typical MII register write access. The frame structure and general read and write transactions are shown in Table 7-6, Figure 7-12, and Figure 7-13.
| TYPICAL MDIO FRAME FORMAT | <idle><start><op code><device addr><reg addr><turnaround><data<<idle> |
|---|---|
| Read Operation | <idle><01><10><AAAA><RRRR><Z0><xxxx xxxx xxxx xxxx><idle> |
| Write Operation | <idle><01<01><AAAA><RRRR><10><xxxx xxxx xxxx xxxx><idle> |
Figure 7-12 Typical MDC/MDIO Read Operation
Figure 7-13 Typical MDC/MDIO Write Operation