ZHCSC07E December 2013 – March 2019 DLPC2607
PRODUCTION DATA.
請參考 PDF 數據表獲取器件具體的封裝圖。
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| ƒclock | Clock frequency, DMD_DCLK and DMD_SAC_CLK(1) | 76.175 | 76.206 | MHz | |
| tp_clkper | Clock period, DMD_DCLK and DMD_SAC_CLK | 50% reference points | 13.122 | 13.128 | ns |
| tp_wh | Pulse duration low, DMD_DCLK and DMD_SAC_CLK | 50% reference points | 6.2 | ns | |
| tp_wl | Pulse duration high, DMD_DCLK and DMD_SAC_CLK | 50% reference points | 6.2 | ns | |
| tt | Transition time – all signals | 20% to 80% reference points | 0.3 | 2 | ns |
| tp_su | Output setup time – DMD_D(14:0),
DMD_SCTRL, DMD_LOADB and DMD_TRC relative to both rising and falling edges of DMD_DCLK(2)(4) |
50% reference points | 1.5 | ns | |
| tp_h | Output hold time – DMD_D(14:0),
DMD_SCTRL,DMD_LOADB and DMD_TRC signals relative to both rising and falling edges of DMD_DCLK(2)(4) |
50% reference points | 1.5 | ns | |
| tp_d1_skew | DMD data skew – DMD_D(14:0),
DMD_SCTRL, DMD_LOADB, and DMD_TRC signals relative to each other(3) |
50% reference points | 0.2 | ns | |
| tp_clk_skew | Clock skew – DMD_DCLK and DMD_SAC_CLK relative to each other | 50% reference points | 0.2 | ns | |
| tp_d2_skew | DAD/SAC data skew - DMD_SAC_BUS,
DMD_DRC_OEZ(6), DMD_DRC_BUS, and DMD_DRC_STRB signals relative to DMD_SAC_CLK |
50% reference points | 0.2 | ns | |