ZHCSOO6C August 2000 – August 2021 DCV010505 , DCV010505D , DCV010512 , DCV010512D , DCV010515 , DCV010515D , DCV011512D , DCV011515D , DCV012405 , DCV012415D
PRODUCTION DATA
Each of the DCV01 series devices can be disabled or enabled by driving the SYNCIN pin using an open-drain CMOS gate. If the SYNCIN pin is pulled low, the DCV01 becomes disabled. The disable time depends upon the external loading. The internal disable function is implemented in 2 μs. Removal of the pulldown causes the DCV01 to be enabled.
Capacitive loading on the SYNCIN pin must be minimized (≤ 3 pF) in order to prevent a reduction in the oscillator frequency. The External Synchronization of the DCP01/02 Series of DC/DC Converters application report (SBAA035) describes disable/enable control circuitry.