ZHCSJP7I December 2000 – September 2020 DCP010505B , DCP010505DB , DCP010507DB , DCP010512B , DCP010512DB , DCP010515B , DCP010515DB , DCP011512DB , DCP011515DB , DCP012405B , DCP012415DB
PRODUCTION DATA
Each of the DCP01B series devices can be disabled or enabled by driving the SYNCIN pin using an open-drain CMOS gate. If the SYNCIN pin is pulled low, the DCP01B becomes disabled. The disable time depends upon the external loading. The internal disable function is implemented within 2 μs. Removal of the pulldown causes the DCP01B to be enabled.
Capacitive loading on the SYNCIN pin must be minimized (≤ 3 pF) to prevent a reduction in the oscillator frequency. The application report External Synchronization of the DCP01/02 Series of DC/DC Converters describes disable and enable control circuitry.