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SCAS878C May 2009 – January 2016 CDCLVP2108

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RGZ|48
- MPQF123F

散熱焊盤機械數據 (封裝 | 引腳)

RGZ|48
- QFND131R

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_CC	Supply voltage⁽²⁾	–0.5	4.6	V
V_IN	Input voltage⁽³⁾	–0.5	V_CC+ 0.5	V
V_OUT	Output voltage⁽³⁾	–0.5	V_CC + 0.5	V
I_IN	Input current		20	mA
I_OUT	Output current		50	mA
T_A	Specified free-air temperature (no airflow)	–40	85	°C
T_J	Maximum junction temperature		125	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All supply voltages must be supplied simultaneously.

(3) The input and output negative voltage ratings may be exceeded if the input clamp-current and output clamp-current ratings are observed.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_CC	Supply voltage	2.375	2.50/3.30	3.60	V
T_A	Ambient temperature	–40		85	°C
T_PCB	PCB temperature (measured at thermal pad)			105	°C

6.4 Thermal Information

See ⁽²⁾⁽³⁾

THERMAL METRIC⁽¹⁾			CDCLVP2108	UNIT
			RGZ (VQFN)
			48 PINS
R_θJA	Junction-to-ambient thermal resistance	0 LFM	30.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance		18.2	°C/W
R_θJB	Junction-to-board thermal resistance		8.3	°C/W
ψ_JT	Junction-to-top characterization parameter		0.5	°C/W
ψ_JB	Junction-to-board characterization parameter		8.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance		3.8	°C/W
θ_JP ⁽⁴⁾	Thermal resistance, junction-to-pad		3.67	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

(2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC 2S2P (high-K board).

(3) Connected to GND with 16 thermal vias (0.3-mm diameter).

(4) R_θJP (junction-to-pad) is used for the VQFN package, because the primary heat flow is from the junction to the GND pad of the VQFN package.

6.5 Electrical Characteristics: LVCMOS Input, at V_CC = 2.375 V to 3.6 V

at T_A = –40°C to +85°C and T_PCB ≤ 105°C (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_IN	Input frequency				200	MHz
V_th	Input threshold voltage	External threshold voltage applied to complementary input	1.1		1.8	V
V_IH	Input high voltage		V_th + 0.1		V_CC	V
V_IL	Input low voltage		0		V_th – 0.1	V
I_IH	Input high current	V_CC= 3.6 V, V_IH = 3.6 V			40	μA
I_IL	Input low current	V_CC= 3.6 V, V_IL = 0 V			–40	μA
ΔV/ΔT	Input edge rate	20% to 80%	1.5			V/ns
I_CAP	Input capacitance			5		pF

(1) Figure 5 and Figure 6 show DC test setup.

6.6 Electrical Characteristics: Differential Input, at V_CC = 2.375 V to 3.6 V

at T_A = –40°C to +85°C and T_PCB ≤ 105°C (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_IN	Input frequency	Clock input			2000	MHz
V_{IN, DIFF, PP}	Differential input peak-peak voltage	f_IN ≤ 1.5 GHz	0.1		1.5	V
V_{IN, DIFF, PP}	Differential input peak-peak voltage	1.5 GHz ≤ f_IN ≤ 2 GHz	0.2		1.5	V
V_ICM	Input common-mode level		1		V_CC – 0.3	V
I_IH	Input high current	V_CC= 3.6 V, V_IH = 3.6 V			40	μA
I_IL	Input low current	V_CC= 3.6 V, V_IL = 0 V			–40	μA
ΔV/ΔT	Input edge rate	20% to 80%	1.5			V/ns
I_CAP	Input capacitance			5		pF

(1) Figure 7 and Figure 8 show DC test setup. Figure 9 shows AC test setup.

6.7 Electrical Characteristics: LVPECL Output, at V_CC = 2.375 V to 2.625 V

at T_A = –40°C to +85°C and T_PCB ≤ 105°C (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_OH	Output high voltage	T_A ≤ 85°C	V_CC – 1.26	V_CC – 0.9	V
V_OH	Output high voltage	T_PCB ≤105°C	V_CC – 1.26	V_CC – 0.83	V
V_OL	Output low voltage	T_A ≤ 85°C	V_CC – 1.7	V_CC – 1.3	V
V_OL	Output low voltage	T_PCB ≤105°C	V_CC – 1.7	V_CC – 1.25	V
V_{OUT, DIFF, PP}	Differential output peak-peak voltage	f_IN ≤ 2 GHz	0.5	1.35	V
V_{AC_REF}	Input bias voltage⁽²⁾	I_{AC_REF} = 2 mA	V_CC – 1.6	V_CC – 1.1	V
I_EE	Supply internal current	Outputs unterminated, T_A ≤ 85°C		115	mA
I_EE	Supply internal current	Outputs unterminated, T_PCB≤ 105ºC		117	mA
I_CC	Output and internal supply current	All outputs terminated, 50 Ω to V_CC – 2 T_A ≤ 85°C		620	mA
I_CC	Output and internal supply current	All outputs terminated, 50 Ω to V_CC – 2 T_PCB≤ 105ºC		677	mA

(1) Figure 10 and Figure 11 show DC and AC test setup.

(2) Internally generated bias voltage (V_{AC_REF}) is for 3.3-V operation only. TI recommends applying externally generated bias voltage for V_CC < 3 V.

6.8 Electrical Characteristics: LVPECL Output, at V_CC = 3 V to 3.6 V

at T_A = –40°C to +85°C and T_PCB ≤ 105°C (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_OH	Output high voltage	T_A ≤ 85°C	V_CC – 1.26	V_CC – 0.9	V
V_OH	Output high voltage	T_PCB≤ 105ºC	V_CC – 1.26	V_CC – 0.85	V
V_OL	Output low voltage	T_A ≤ 85°C	V_CC – 1.7	V_CC – 1.3	V
V_OL	Output low voltage	T_PCB≤ 105ºC	V_CC – 1.7	V_CC – 1.3	V
V_{OUT, DIFF, PP}	Differential output peak-peak voltage	f_IN ≤ 2 GHz	0.65	1.35	V
V_{AC_REF}	Input bias voltage	I_{AC_REF} = 2 mA	V_CC – 1.6	V_CC – 1.1	V
I_EE	Supply internal current	Outputs unterminated, T_A ≤ 85°C		115	mA
I_EE	Supply internal current	Outputs unterminated, T_PCB≤ 105ºC		117	mA
I_CC	Output and internal supply current	All outputs terminated, 50 Ω to V_CC – 2 T_A ≤ 85°C		620	mA
I_CC	Output and internal supply current	All outputs terminated, 50 Ω to V_CC – 2 T_PCB≤ 105ºC		677	mA

(1) Figure 10 and Figure 11 show DC and AC test setup.

(2) 100-MHz Wenzel oscillator, Input slew rate = 0.9 V/ns (single-ended)

(3) 100-MHz Wenzel oscillator, Input slew rate = 3.4 V/ns (differential)

(4) 122.88-MHz Rohde & Schwarz SMA100A, Input slew rate = 3.7 V/ns (differential)

(5) 156.25-MHz Crystek CPRO33 oscillator, Input slew rate = 2.9 V/ns (differential)

(6) 312.5-MHz Rohde & Schwarz SMA100A, Input slew rate = 4 V/ns (differential)

6.9 Timing Requirements, at V_CC = 2.375 V to 2.625 V

Refer to Figure 1 and Figure 2.

			MIN	NOM	MAX	UNIT
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.1 V			550	ps
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.3 V			550	ps
t_SK,PP	Part-to-part skew				150	ps
t_{SK,O_WB}	Within bank output skew	Both inputs have equal skew			25	ps
t_{SK,O_BB}	Bank-to-bank output skew	Crossing-point-to-crossing-point distortion, f_OUT = 100 MHz			30	ps
t_SK,P	Pulse skew (with 50% duty cycle input)		–50		50	ps
t_RJIT	Random additive jitter (with 50% duty cycle input)	f_OUT = 100 MHz, V_IN,SE = V_CC, V_th = 1.25 V, 10 kHz to 20 MHz		0.124		ps, RMS
		f_OUT = 100 MHz, V_IN,SE = 0.9 V, V_th = 1.1 V, 10 kHz to 20 MHz		0.178		ps, RMS
		f_OUT = 2 GHz, V_IN,DIFF,PP = 0.2 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.061		ps, RMS
		f_OUT = 100 MHz, V_IN,DIFF,PP = 0.15 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.119		ps, RMS
		f_OUT = 100 MHz, V_IN,DIFF,PP = 1 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.104		ps, RMS
		f_OUT,8 = 500 MHz, V_IN,DIFF,PP,0 = 0.15 V, V_{ICM, 0} = 1 V, f_{OUT, 7} = 62.5 MHz, V_IN,SE,1 = V_CC, V_{th, 1} = V_CC/2		–46.6		dBc
P_SPUR	Coupling on differential OUT8 from OUT7 in the frequency spectrum of f_{OUT, 8} ±(f_{OUT, 8}/2) with synchronous inputs	f_OUT,8 = 500 MHz, V_IN,DIFF,PP,0 = 0.15 V, V_{ICM, 0} = 1 V, f_{OUT, 7} = 62.5 MHz, V_IN,DIFF,PP,1 = 1 V, V_{ICM, 1} = 1 V		–49.1		dBc
		f_OUT,8 = 500 MHz, V_IN,DIFF,PP,0 = 0.15 V, V_{ICM, 0} = 1 V, f_{OUT, 7} = 15.625 MHz, V_IN,SE,1 = V_CC, V_{th, 1} = V_CC/2		–61
		f_OUT,8 = 500 MHz, V_IN,DIFF,PP,0 = 0.15 V, V_{ICM, 0} = 1 V, f_{OUT, 7} = 15.625 MHz, V_IN,DIFF,PP,1 = 1 V, V_{ICM, 1} = 1 V		–62.5
t_R/t_F	Output rise/fall time	20% to 80%			200	ps

6.10 Timing Requirements, at V_CC = 3 V to 3.6 V

Refer to Figure 1 and Figure 2.

			MIN	NOM	MAX	UNIT
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.1 V			550	ps
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.3 V			550	ps
t_SK,PP	Part-to-part skew				150	ps
t_{SK,O_WB}	Within bank output skew				25	ps
t_{SK,O_BB}	Bank-to-bank output skew	Both inputs have equal skew			30	ps
t_SK,P	Pulse skew (with 50% duty cycle input)	Crossing-point-to-crossing-point distortion, f_OUT = 100 MHz	–50		50	ps
t_RJIT	Random additive jitter (with 50% duty cycle input)	f_OUT = 100 MHz,⁽²⁾ V_IN,SE = V_CC, V_th = 1.65 V, 10 kHz to 20 MHz		0.121		ps, RMS
		f_OUT = 100 MHz,⁽²⁾ V_IN,SE = 0.9 V, V_th = 1.1 V, 10 kHz to 20 MHz		0.185		ps, RMS
		f_OUT = 2 GHz, V_IN,DIFF,PP = 0.2 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.077		ps, RMS
		f_OUT = 100 MHz,⁽²⁾ V_IN,DIFF,PP = 0.15 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.122		ps, RMS
		f_OUT = 100 MHz,⁽²⁾ V_IN,DIFF,PP = 1 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.105		ps, RMS
		f_OUT,8 = 500 MHz, V_IN,DIFF,PP,0 = 0.15 V, V_{ICM, 0} = 1 V, f_{OUT, 7} = 62.5 MHz, V_IN,SE,1 = V_CC, V_{th, 1} = V_CC/2		–48.5		dBc
		f_OUT = 100 MHz⁽³⁾, Input AC-coupled, V_ICM = V_{AC_REF}, 12 kHz to 20 MHz		0.068		ps, RMS
		f_OUT = 122.88 MHz⁽⁴⁾, Input AC-coupled, V_ICM = V_{AC_REF}, 12 kHz to 20 MHz		0.056		ps, RMS
		f_OUT = 156.25 MHz⁽⁵⁾, Input AC-coupled, V_ICM = V_{AC_REF}, 12 kHz to 20 MHz		0.047		ps, RMS
		f_OUT = 312.5 MHz⁽⁶⁾, Input AC-coupled, V_ICM = V_{AC_REF}, 12 kHz to 20 MHz		0.026		ps, RMS
P_SPUR	Coupling on differential OUT8 from OUT7 in the frequency spectrum of f_{OUT, 8} ±(f_{OUT, 8}/2) with synchronous inputs	f_OUT,8 = 500 MHz, V_IN,DIFF,PP,0 = 0.15 V, V_{ICM, 0} = 1 V, f_{OUT, 7} = 62.5 MHz, V_IN,SIFF,PP,1 = 1 V, V_{ICM, 1} = 1 V		–50.6		dBc
		f_OUT,8 = 500 MHz, V_IN,DIFF,PP,0 = 0.15 V, V_{ICM, 0} = 1 V, f_{OUT, 7} = 15.625 MHz, V_IN,SE,1 = V_CC, V_{th, 1} = V_CC/2		–60.5		dBc
		f_OUT,8 = 500 MHz, V_IN,DIFF,PP,0 = 0.15 V, V_{ICM, 0} = 1 V, f_{OUT, 7} = 15.625 MHz, V_IN,DIFF,PP,1 = 1 V, V_{ICM, 1} = 1 V		–60.9		dBc
t_R/t_F	Output rise/fall time	20% to 80%			200	ps

Figure 1 shows the output voltage and rise/fall time. Output and part-to-part skew are shown in Figure 2.

Figure 1. Output Voltage and Rise/Fall Time

1. Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest t_PLHn (n = 0, 1, 2....15), or as the difference between the fastest and the slowest t_PHLn (n = 0, 1, 2....15).

2. Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest t_PLHn (n = 0, 1, 2....15) across multiple devices, or the difference between the fastest and the slowest t_PHLn (n = 0, 1, 2....15) across multiple devices.

Figure 2. Output and Part-to-Part Skew

6.11 Typical Characteristics

at T_A = –40°C to +85°C (unless otherwise noted)

CDCLVP2108 tc_fqcy_diff_vout_swing01_cas878.gif

Figure 3. Differential Output Peak-to-Peak Voltage vs Frequency

CDCLVP2108 tc_fqcy_diff_vout_swing02_cas878.gif

Figure 4. Differential Output Peak-to-Peak Voltage vs Frequency

封裝選項

機械數據 (封裝 | 引腳)

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Electrical Characteristics: LVCMOS Input, at VCC = 2.375 V to 3.6 V

6.6 Electrical Characteristics: Differential Input, at VCC = 2.375 V to 3.6 V

6.7 Electrical Characteristics: LVPECL Output, at VCC = 2.375 V to 2.625 V

6.8 Electrical Characteristics: LVPECL Output, at VCC = 3 V to 3.6 V

6.9 Timing Requirements, at VCC = 2.375 V to 2.625 V

6.10 Timing Requirements, at VCC = 3 V to 3.6 V

6.11 Typical Characteristics

6.5 Electrical Characteristics: LVCMOS Input, at V_CC = 2.375 V to 3.6 V

6.6 Electrical Characteristics: Differential Input, at V_CC = 2.375 V to 3.6 V

6.7 Electrical Characteristics: LVPECL Output, at V_CC = 2.375 V to 2.625 V

6.8 Electrical Characteristics: LVPECL Output, at V_CC = 3 V to 3.6 V

6.9 Timing Requirements, at V_CC = 2.375 V to 2.625 V

6.10 Timing Requirements, at V_CC = 3 V to 3.6 V