12 Revision History

Changes from Revision D (June 2019) to Revision E (October 2019)

• 刪除了數據表中的分數輸出分頻器 (FOD) 和展頻時鐘 (SSC) 信息Go
• Added footnote to Timing Characteristics table Go
• Removed FOD from Functional Block Diagram Go
• Changed REFSEL selection from L to H.Go
• Removed Output Channel Divider Types and Delay table Go
• Removed the FOD control bits in the Power Management graphicGo
• Added Page-mode EEPROM read instructionsGo
• Changed Pre-Configured EEPROM Page 0 graphicGo
• Changed Pre-Configured EEPROM Page 1 graphicGo
• Added additional details on pullup resistor and load capacitor added to power-up sequenceGo
• Removed fractional output divider information from the registers Go
• Removed FOD information from the CDCI6214 Registers tableGo

Changes from Revision C (November 2018) to Revision D (June 2019)

• Added VDDREF and tablenote to the output supply voltage parameter in the Recommended Operating Conditions Go
• Added statement on chX_1p8vdet setting Go
• Changed CDCI6214 - Pre-Configured EEPROM Page 0 graphicGo

Changes from Revision B (April 2018) to Revision C (November 2018)

• Changed pin names for pins 1 and 2 from: XIN and XOUT to: XOUT/FB_P and XIN/FB_N.Go
• Changed descriptions for pins 1 and 2Go
• Changed pin names for pins 1 and 2 in #GUID-FFC11261-A157-480F-A1A3-31A56ED88FB5/TITLE-SNAS690SNAS6908516_3 Go
• Changed pin names for pins 1 and 2 in #GUID-FA6F37A7-22A5-4625-AB38-51BC5813B88F/TITLE-SNAS690SNAS6902663_4 Go
• Changed Input capacitance specification symbols in #GUID-FA6F37A7-22A5-4625-AB38-51BC5813B88F/TITLE-SNAS690SNAS6902663_4 from: C_{IN_XOUT} and C_{IN_XIN} to: C_{IN_XOUT/FB_P} and C_{IN_XIN/FB_P} Go
• Changed pins 1 and 2 from: XIN and XOUT to: XOUT/FB_P and XIN/FB_N in the Functional Block Diagram Go
• Changed pins 1 and 2 from: XIN and XOUT to: XOUT/FB_P and XIN/FB_N in the Reference Block graphicGo
• Changed External (XIN) pin to: FB_P/N in the Phase-Locked Loop Circuit graphicGo
• Changed pins 1 and 2 from: XIN and XOUT to: XOUT/FB_P and XIN/FB_N in the CDCI6214 - Pre-Configured EEPROM Page 0 and CDCI6214 - Pre-Configured EEPROM Page 1 graphicsGo
• Changed pins XIN and XOUT to: XOUT/FB_P and XIN/FB_N in the Typical Applications schematicsGo
• Changed design parameter superscript to a subscript Go

Changes from Revision A (October 2017) to Revision B (April 2018)

• Changed pinout pins 5 and 6 from NC to REFP, REFN inputs.Go
• Changed supply voltage maximum from: 3.6 V to: 3.65 VGo
• Removed Skew between HCSL maximum from the #GUID-0EC6482D-E2C4-46BB-8BD5-3F5A804E4866/TITLE-SNAS690SNAS6905705_3 tableGo

Changes from Revision * (July 2017) to Revision A (October 2017)

• 將器件狀態從“預告信息”更改為“量產數據”Go
• Changed REFSEL pin description to reflext REFMUX control. Go