VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and TA = –40°C to 85°C| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|
| tINIT | Initialization time(3) | Initialization time from POR to device releasing PLL outputs. | | | 5 | ms |
| tVDD | Power supply ramp(1)(2) | Timing requirement for any VDD pin while RESETN = LOW | 50 | | 2000 | μs |
(1) RESETN pin should be LOW until VDD reaches 95% of final value. TI recommends adding a pullup resistor of 4.7 kΩ and a capacitance of 0.47 μF to Ground on RESETN pin to meet the POR timing requirement.
(2) After supply is settled within ±5% of target value, the initial rising edge on
RESETN will start internal logic.
(3) tINIT = tEELOAD+ tSTAB