11 Revision History
Changes from Revision H (February 2024) to Revision I (August 2024)
- 向應(yīng)用列表添加了鏈接Go
- Updated footnote language to conform to updated TI Datasheet Guidelines throughout
the Specifications sectionGo
- Updated Power Supply Recommendations
section with correct power sequenceGo
Changes from Revision G (October 2016) to Revision H (February 2024)
- 更新了整個文檔中的表格、圖和交叉參考的編號格式Go
- 將提到 I2C 的舊術(shù)語實例通篇更改為控制器和目標Go
- 將器件信息 表更改為封裝信息
Go
- Changed unit kbit/s to kbpsGo
- Added information on allowable data inputs during the EEPROM write cycle in Data Protocol
Go
Changes from Revision F (April 2015) to Revision G (October 2016)
- 將數(shù)據(jù)表標題從CDCEx913 具有 1.8V、2.5V 和 3.3V 輸出的可編程 1-PLL VCXO 時鐘合成器 更改為：CDCE(L)913：支持 SSC 以降低 EMI 的靈活低功耗 LVCMOS 時鐘發(fā)生器
Go
Changes from Revision E (March 2010) to Revision F (April 2015)
- 添加了 ESD 等級 表、特性說明 部分、器件功能模式、應(yīng)用和實施 部分、電源相關(guān)建議 部分、布局 部分、器件和文檔支持 部分以及機械、封裝和可訂購信息 部分Go
- Added in Figure 9, second S to SrGo
- Changed 100 MHz < ?VCO > 200 MHz; TO 80 MHz ≤ ?VCO ≤ 230 MHz; and changed 0 ≤ p ≤ 7 TO 0 ≤ p ≤ 4Go
- Changed under Example, fifth row, N", 2 places TO N'Go
Changes from Revision D (October 2009) to Revision E (March 2010)
- Added PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511 to PLL Multiplier/Divider Definition SectionGo
- Added PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096 foot to PLL1 Configure Register TableGo
Changes from Revision C (August 2007) to Revision D (October 2009)
- Deleted sentence - A different default setting can be programmed upon customer request. Contact Texas Instruments sales or marketing representative for more information.Go