ZHCSPD1D February 1998 – November 2021 CD54HC165 , CD54HCT165 , CD74HC165 , CD74HCT165
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The ’HC165 and ’HCT165 are 8-bit parallel or serial-in shift registers with complementary serial outputs (QH and QH) available from the last stage. When the parallel load (SH/LD) input is LOW, parallel data from the A to H inputs are loaded into the register asynchronously. When the SH/LD is HIGH, data enters the register serially at the SER input and shifts one place to the right (A→B→C, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by connecting the QH output to the SER input of the succeeding device.
For predictable operation the LOW-to-HIGH transition of CLK INH should only take place while CLK is HIGH. Also, CLK and CLK INH should be LOW before the LOW-to-HIGH transition of SH/LD to prevent shifting the data when SH/LD goes HIGH.