ZHCSLH5K August 1998 – June 2020 CD4049UB , CD4050B
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
Figure 5-1 CD4049UB D, DW, N, NS, and PW Packages
16-Pin SOIC, PDIP, SO, and TSSOP
Top View
Figure 5-2 CD4050B
D, DW, N, NS, and PW Packages
1G6-Pin SOIC, PDIP, SO, and TSSOP
Top View| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| A | 3 | I | Input 1 |
| B | 5 | I | Input 2 |
| C | 7 | I | Input 3 |
| D | 9 | I | Input 4 |
| E | 11 | I | Input 5 |
| F | 14 | I | Input 6 |
| G | 2 | O | Inverting output 1. G = A |
| H | 4 | O | Inverting output 2. H = B |
| I | 6 | O | Inverting output 3. I = C |
| J | 10 | O | Inverting output 4. J = D |
| K | 12 | O | Inverting output 5. K = E |
| L | 15 | O | Inverting output 6. L = F |
| NC | 13, 16 | — | No connection |
| VCC | 1 | — | Power pin |
| VSS | 8 | — | Negative supply |
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| A | 3 | I | Input 1 |
| B | 5 | I | Input 2 |
| C | 7 | I | Input 3 |
| D | 9 | I | Input 4 |
| E | 11 | I | Input 5 |
| F | 14 | I | Input 6 |
| G | 2 | O | Inverting output 1. G = A |
| H | 4 | O | Inverting output 2. H = B |
| I | 6 | O | Inverting output 3. I = C |
| J | 10 | O | Inverting output 4. J = D |
| K | 12 | O | Inverting output 5. K = E |
| L | 15 | O | Inverting output 6. L = F |
| NC | 13, 16 | — | No connection |
| VCC | 1 | — | Power pin |
| VSS | 8 | — | Negative supply |