ZHCS896I May 2009 – September 2018 CC430F5133 , CC430F5135 , CC430F5137 , CC430F6125 , CC430F6126 , CC430F6127 , CC430F6135 , CC430F6137
PRODUCTION DATA.
- 1器件概述
- 2修訂歷史記錄
- 3Device Comparison
- 4Terminal Configuration and Functions
-
5Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Active Mode Supply Current Into VCC Excluding External Current
- 5.5 Typical Characteristics – Active Mode Supply Currents
- 5.6 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
- 5.7 Typical Characteristics – Low-Power Mode Supply Currents
- 5.8 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
- 5.9 Thermal Resistance Characteristics, CC430F51xx
- 5.10 Thermal Resistance Characteristics, CC430F61xx
- 5.11 Digital Inputs
- 5.12 Digital Outputs
- 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
- 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
- 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
- 5.16 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
- 5.17 Internal Reference, Low-Frequency Oscillator (REFO)
- 5.18 DCO Frequency
- 5.19 PMM, Brownout Reset (BOR)
- 5.20 PMM, Core Voltage
- 5.21 PMM, SVS High Side
- 5.22 PMM, SVM High Side
- 5.23 PMM, SVS Low Side
- 5.24 PMM, SVM Low Side
- 5.25 Wake-up Times From Low-Power Modes and Reset
- 5.26 Timer_A
- 5.27 USCI (UART Mode) Clock Frequency
- 5.28 USCI (UART Mode)
- 5.29 USCI (SPI Master Mode) Clock Frequency
- 5.30 USCI (SPI Master Mode)
- 5.31 USCI (SPI Slave Mode)
- 5.32 USCI (I2C Mode)
- 5.33 LCD_B Operating Conditions
- 5.34 LCD_B Electrical Characteristics
- 5.35 12-Bit ADC, Power Supply and Input Range Conditions
- 5.36 12-Bit ADC, Timing Parameters
- 5.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
- 5.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
- 5.39 12-Bit ADC, Temperature Sensor and Built-In VMID
- 5.40 REF, External Reference
- 5.41 REF, Built-In Reference
- 5.42 Comparator_B
- 5.43 Flash Memory
- 5.44 JTAG and Spy-Bi-Wire Interface
- 5.45
RF1A CC1101-Based Radio Parameters
- 5.45.1 Recommended Operating Conditions
- 5.45.2 RF Crystal Oscillator, XT2
- 5.45.3 Current Consumption, Reduced-Power Modes
- 5.45.4 Current Consumption, Receive Mode
- 5.45.5 Current Consumption, Transmit Mode
- 5.45.6 Typical TX Current Consumption, 315 MHz
- 5.45.7 Typical TX Current Consumption, 433 MHz
- 5.45.8 Typical TX Current Consumption, 868 MHz
- 5.45.9 Typical TX Current Consumption, 915 MHz
- 5.45.10 RF Receive, Overall
- 5.45.11 RF Receive, 315 MHz
- 5.45.12 RF Receive, 433 MHz
- 5.45.13 RF Receive, 868 or 915 MHz
- 5.45.14 Typical Sensitivity, 315 MHz, Sensitivity Optimized Setting
- 5.45.15 Typical Sensitivity, 433 MHz, Sensitivity Optimized Setting
- 5.45.16 Typical Sensitivity, 868 MHz, Sensitivity Optimized Setting
- 5.45.17 Typical Sensitivity, 915 MHz, Sensitivity Optimized Setting
- 5.45.18 RF Transmit
- 5.45.19 Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
- 5.45.20 Typical Output Power, 315 MHz
- 5.45.21 Typical Output Power, 433 MHz
- 5.45.22 Typical Output Power, 868 MHz
- 5.45.23 Typical Output Power, 915 MHz
- 5.45.24 Frequency Synthesizer Characteristics
- 5.45.25 Typical RSSI_offset Values
-
6Detailed Description
- 6.1 Sub-1 GHz Radio
- 6.2 CPU
- 6.3 Operating Modes
- 6.4 Interrupt Vector Addresses
- 6.5 Memory Organization
- 6.6 Bootloader (BSL)
- 6.7 JTAG Operation
- 6.8 Flash Memory
- 6.9 RAM
- 6.10
Peripherals
- 6.10.1 Oscillator and System Clock
- 6.10.2 Power-Management Module (PMM)
- 6.10.3 Digital I/O
- 6.10.4 Port Mapping Controller
- 6.10.5 System Module (SYS)
- 6.10.6 DMA Controller
- 6.10.7 Watchdog Timer (WDT_A)
- 6.10.8 CRC16
- 6.10.9 Hardware Multiplier
- 6.10.10 AES128 Accelerator
- 6.10.11 Universal Serial Communication Interface (USCI)
- 6.10.12 TA0
- 6.10.13 TA1
- 6.10.14 Real-Time Clock (RTC_A)
- 6.10.15 Voltage Reference (REF)
- 6.10.16 LCD_B (Only CC430F613x and CC430F612x)
- 6.10.17 Comparator_B
- 6.10.18 ADC12_A (Only CC430F613x and CC430F513x)
- 6.10.19 Embedded Emulation Module (EEM) (S Version)
- 6.10.20 Peripheral File Map
- 6.11
Input/Output Diagrams
- 6.11.1 Port P1 (P1.0 to P1.4) Input/Output With Schmitt Trigger
- 6.11.2 Port P1 (P1.5 to P1.7) Input/Output With Schmitt Trigger
- 6.11.3 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
- 6.11.4 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
- 6.11.5 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only)
- 6.11.6 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
- 6.11.7 Port P5 (P5.2 to P5.4) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only)
- 6.11.8 Port P5 (P5.5 to P5.7) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only)
- 6.11.9 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
- 6.11.10 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
- 6.12 Device Descriptor
- 7Applications, Implementation, and Layout
- 8器件和文檔支持
- 9機械，封裝和可訂購信息
5.45.13 RF Receive, 868 or 915 MHz
TA = 25°C, VCC = 3 V (unless otherwise noted)(1)1% packet error rate, 20-byte packet length, Sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF = 0 (unless otherwise noted)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| 0.6-kBaud data rate, 2-FSK, 14.3-kHz deviation, 58-kHz digital channel filter bandwidth (unless otherwise noted) | ||||||
| Receiver sensitivity | –115 | dBm | ||||
| 1.2-kBaud data rate, 2-FSK, 5.2-kHz deviation, 58-kHz digital channel filter bandwidth (unless otherwise noted) | ||||||
| Receiver sensitivity(1) | –109 | dBm | ||||
| 2-GFSK modulation by setting MDMCFG2.MOD_FORMAT = 2,
Gaussian filter with BT = 0.5 |
–109 | |||||
| Saturation | FIFOTHR.CLOSE_IN_RX =0(3) | –28 | dBm | |||
| Adjacent channel rejection | Desired channel 3 dB above the sensitivity limit, 100-kHz channel spacing(2) | –100-kHz offset | 39 | dB | ||
| +100-kHz offset | 39 | |||||
| Image channel rejection | IF 152 kHz, desired channel 3 dB above the sensitivity limit | 29 | dB | |||
| Blocking | Desired channel 3 dB above the sensitivity limit(4) | ±2-MHz offset | –48 | dBm | ||
| ±10-MHz offset | –40 | dBm | ||||
| 38.4-kBaud data rate, 2-FSK, 20-kHz deviation, 100-kHz digital channel filter bandwidth (unless otherwise noted) | ||||||
| Receiver sensitivity(5) | –102 | dBm | ||||
| 2-GFSK modulation by setting MDMCFG2.MOD_FORMAT = 2,
Gaussian filter with BT = 0.5 |
–101 | |||||
| Saturation | FIFOTHR.CLOSE_IN_RX =0(3) | –19 | dBm | |||
| Adjacent channel rejection | Desired channel 3 dB above the sensitivity limit, 200-kHz channel spacing(4) | –200-kHz offset | 20 | dB | ||
| +200-kHz offset | 25 | |||||
| Image channel rejection | IF 152 kHz, desired channel 3 dB above the sensitivity limit | 23 | dB | |||
| Blocking | Desired channel 3 dB above the sensitivity limit(4) | ±2-MHz offset | –48 | dBm | ||
| ±10-MHz offset | –40 | dBm | ||||
| 250-kBaud data rate, 2-FSK, 127-kHz deviation, 540-kHz digital channel filter bandwidth (unless otherwise noted) | ||||||
| Receiver sensitivity (7) | –90 | dBm | ||||
| 2-GFSK modulation by setting MDMCFG2.MOD_FORMAT = 2,
Gaussian filter with BT = 0.5 |
–90 | |||||
| Saturation | FIFOTHR.CLOSE_IN_RX =0(3) | –19 | dBm | |||
| Adjacent channel rejection | Desired channel 3 dB above the sensitivity limit, 750-kHz channel spacing(6) | –750-kHz offset | 24 | dB | ||
| +750-kHz offset | 30 | |||||
| Image channel rejection | IF 304 kHz, desired channel 3 dB above the sensitivity limit | 18 | dB | |||
| Blocking | Desired channel 3 dB above the sensitivity limit(6) | ±2-MHz offset | –53 | dBm | ||
| ±10-MHz offset | –39 | dBm | ||||
| 500-kBaud data rate, MSK, 812-kHz digital channel filter bandwidth (unless otherwise noted) | ||||||
| Receiver sensitivity(7) | –84 | dBm | ||||
| Image channel rejection | IF 355 kHz, desired channel 3 dB above the sensitivity limit | –2 | dB | |||
| Blocking | Desired channel 3 dB above the sensitivity limit(8) | ±2-MHz offset | –53 | dBm | ||
| ±10-MHz offset | –38 | dBm | ||||
(1) Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF =1. The typical current consumption is then reduced by approximately 2 mA close to the sensitivity limit. The sensitivity is typically reduced to –107 dBm
(2) See Figure 5-21 for blocking performance at other offset frequencies.
(3) See DN010 Close-in Reception with CC1101.
(4) See Figure 5-22 for blocking performance at other offset frequencies.
(5) Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF =1. The typical current consumption is then reduced by approximately 2 mA close to the sensitivity limit. The sensitivity is typically reduced to –100 dBm.
(6) See Figure 5-23 for blocking performance at other offset frequencies.
(7) MDMCFG2.DEM_DCFILT_OFF = 1 cannot be used for data rates ≥ 250kBaud.
(8) See Figure 5-24 for blocking performance at other offset frequencies.
A.
Figure 5-21 Typical Selectivity at 1.2-kBaud Data Rate NOTE:
868.3 MHz, 2-FSK, 5.2-kHz deviation, IF is 152.3 kHz, digital channel filter bandwidth is 58 kHz
A.
Figure 5-22 Typical Selectivity at 38.4-kBaud Data Rate NOTE:
868 MHz, 2-FSK, 20 kHz deviation, IF is 152.3 kHz, digital channel filter bandwidth is 100 kHz
A.
Figure 5-23 Typical Selectivity at 250-kBaud Data Rate NOTE:
868 MHz, 2-FSK, IF is 304 kHz, digital channel filter bandwidth is 540 kHz
A.
Figure 5-24 Typical Selectivity at 500-kBaud Data Rate NOTE:
868 MHz, 2-FSK, IF is 355 kHz, digital channel filter bandwidth is 812 kHz