ZHCS896I May 2009 – September 2018 CC430F5133 , CC430F5135 , CC430F5137 , CC430F6125 , CC430F6126 , CC430F6127 , CC430F6135 , CC430F6137
PRODUCTION DATA.
Table 6-12 lists the base address for the registers of each peripheral.
| MODULE NAME | BASE ADDRESS | OFFSET ADDRESS RANGE |
|---|---|---|
| Special Functions (see Table 6-13) | 0100h | 000h–01Fh |
| PMM (see Table 6-14) | 0120h | 000h–00Fh |
| Flash Control (see Table 6-15) | 0140h | 000h–00Fh |
| CRC16 (see Table 6-16) | 0150h | 000h–007h |
| RAM Control (see Table 6-17) | 0158h | 000h–001h |
| Watchdog (see Table 6-18) | 015Ch | 000h–001h |
| UCS (see Table 6-19) | 0160h | 000h–01Fh |
| SYS (see Table 6-20) | 0180h | 000h–01Fh |
| Shared Reference (see Table 6-21) | 01B0h | 000h–001h |
| Port Mapping Control (see Table 6-22) | 01C0h | 000h–007h |
| Port Mapping Port P1 (see Table 6-23) | 01C8h | 000h–007h |
| Port Mapping Port P2 (see Table 6-24) | 01D0h | 000h–007h |
| Port Mapping Port P3 (see Table 6-25) | 01D8h | 000h–007h |
| Port P1, P2 (see Table 6-26) | 0200h | 000h–01Fh |
| Port P3, P4 (see Table 6-27)
(P4 not available on CC430F513x) |
0220h | 000h–01Fh |
| Port P5 (see Table 6-28) | 0240h | 000h–01Fh |
| Port PJ (see Table 6-29) | 0320h | 000h–01Fh |
| TA0 (see Table 6-30) | 0340h | 000h–03Fh |
| TA1 (see Table 6-31) | 0380h | 000h–03Fh |
| RTC_A (see Table 6-32) | 04A0h | 000h–01Fh |
| 32-Bit Hardware Multiplier (see Table 6-33) | 04C0h | 000h–02Fh |
| DMA Module Control (see Table 6-34) | 0500h | 000h–00Fh |
| DMA Channel 0 (see Table 6-35) | 0510h | 000h–00Fh |
| DMA Channel 1 (see Table 6-36) | 0520h | 000h–00Fh |
| DMA Channel 2 (see Table 6-37) | 0530h | 000h–00Fh |
| USCI_A0 (see Table 6-38) | 05C0h | 000h–01Fh |
| USCI_B0 (see Table 6-39) | 05E0h | 000h–01Fh |
| ADC12 (see Table 6-40)
(only CC430F613x and CC430F513x) |
0700h | 000h–03Fh |
| Comparator_B (see Table 6-41) | 08C0h | 000h–00Fh |
| AES Accelerator (see Table 6-42) | 09C0h | 000h–00Fh |
| LCD_B (see Table 6-43)
(only CC430F613x and CC430F612x) |
0A00h | 000h–05Fh |
| Radio Interface (see Table 6-44) | 0F00h | 000h–03Fh |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| SFR interrupt enable | SFRIE1 | 00h |
| SFR interrupt flag | SFRIFG1 | 02h |
| SFR reset pin control | SFRRPCR | 04h |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| PMM control 0 | PMMCTL0 | 00h |
| PMM control 1 | PMMCTL1 | 02h |
| SVS high side control | SVSMHCTL | 04h |
| SVS low side control | SVSMLCTL | 06h |
| PMM interrupt flags | PMMIFG | 0Ch |
| PMM interrupt enable | PMMIE | 0Eh |
| PMM power mode 5 control | PM5CTL0 | 10h |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| Flash control 1 | FCTL1 | 00h |
| Flash control 3 | FCTL3 | 04h |
| Flash control 4 | FCTL4 | 06h |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| CRC data input | CRC16DI | 00h |
| CRC initialization and result | CRCINIRES | 04h |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| RAM control 0 | RCCTL0 | 00h |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| Watchdog timer control | WDTCTL | 00h |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| UCS control 0 | UCSCTL0 | 00h |
| UCS control 1 | UCSCTL1 | 02h |
| UCS control 2 | UCSCTL2 | 04h |
| UCS control 3 | UCSCTL3 | 06h |
| UCS control 4 | UCSCTL4 | 08h |
| UCS control 5 | UCSCTL5 | 0Ah |
| UCS control 6 | UCSCTL6 | 0Ch |
| UCS control 7 | UCSCTL7 | 0Eh |
| UCS control 8 | UCSCTL8 | 10h |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| System control | SYSCTL | 00h |
| Bootloader configuration area | SYSBSLC | 02h |
| JTAG mailbox control | SYSJMBC | 06h |
| JTAG mailbox input 0 | SYSJMBI0 | 08h |
| JTAG mailbox input 1 | SYSJMBI1 | 0Ah |
| JTAG mailbox output 0 | SYSJMBO0 | 0Ch |
| JTAG mailbox output 1 | SYSJMBO1 | 0Eh |
| Bus error vector generator | SYSBERRIV | 18h |
| User NMI vector generator | SYSUNIV | 1Ah |
| System NMI vector generator | SYSSNIV | 1Ch |
| Reset vector generator | SYSRSTIV | 1Eh |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| Shared reference control | REFCTL | 00h |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| Port mapping key | PMAPKEYID | 00h |
| Port mapping control | PMAPCTL | 02h |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| Port P1.0 mapping | P1MAP0 | 00h |
| Port P1.1 mapping | P1MAP1 | 01h |
| Port P1.2 mapping | P1MAP2 | 02h |
| Port P1.3 mapping | P1MAP3 | 03h |
| Port P1.4 mapping | P1MAP4 | 04h |
| Port P1.5 mapping | P1MAP5 | 05h |
| Port P1.6 mapping | P1MAP6 | 06h |
| Port P1.7 mapping | P1MAP7 | 07h |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| Port P2.0 mapping | P2MAP0 | 00h |
| Port P2.1 mapping | P2MAP1 | 01h |
| Port P2.2 mapping | P2MAP2 | 02h |
| Port P2.3 mapping | P2MAP3 | 03h |
| Port P2.4 mapping | P2MAP4 | 04h |
| Port P2.5 mapping | P2MAP5 | 05h |
| Port P2.6 mapping | P2MAP6 | 06h |
| Port P2.7 mapping | P2MAP7 | 07h |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| Port P3.0 mapping | P3MAP0 | 00h |
| Port P3.1 mapping | P3MAP1 | 01h |
| Port P3.2 mapping | P3MAP2 | 02h |
| Port P3.3 mapping | P3MAP3 | 03h |
| Port P3.4 mapping | P3MAP4 | 04h |
| Port P3.5 mapping | P3MAP5 | 05h |
| Port P3.6 mapping | P3MAP6 | 06h |
| Port P3.7 mapping | P3MAP7 | 07h |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| Port P1 input | P1IN | 00h |
| Port P1 output | P1OUT | 02h |
| Port P1 direction | P1DIR | 04h |
| Port P1 pullup/pulldown enable | P1REN | 06h |
| Port P1 drive strength | P1DS | 08h |
| Port P1 selection | P1SEL | 0Ah |
| Port P1 interrupt vector word | P1IV | 0Eh |
| Port P1 interrupt edge select | P1IES | 18h |
| Port P1 interrupt enable | P1IE | 1Ah |
| Port P1 interrupt flag | P1IFG | 1Ch |
| Port P2 input | P2IN | 01h |
| Port P2 output | P2OUT | 03h |
| Port P2 direction | P2DIR | 05h |
| Port P2 pullup/pulldown enable | P2REN | 07h |
| Port P2 drive strength | P2DS | 09h |
| Port P2 selection | P2SEL | 0Bh |
| Port P2 interrupt vector word | P2IV | 1Eh |
| Port P2 interrupt edge select | P2IES | 19h |
| Port P2 interrupt enable | P2IE | 1Bh |
| Port P2 interrupt flag | P2IFG | 1Dh |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| Port P3 input | P3IN | 00h |
| Port P3 output | P3OUT | 02h |
| Port P3 direction | P3DIR | 04h |
| Port P3 pullup/pulldown enable | P3REN | 06h |
| Port P3 drive strength | P3DS | 08h |
| Port P3 selection | P3SEL | 0Ah |
| Port P4 input | P4IN | 01h |
| Port P4 output | P4OUT | 03h |
| Port P4 direction | P4DIR | 05h |
| Port P4 pullup/pulldown enable | P4REN | 07h |
| Port P4 drive strength | P4DS | 09h |
| Port P4 selection | P4SEL | 0Bh |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| Port P5 input | P5IN | 00h |
| Port P5 output | P5OUT | 02h |
| Port P5 direction | P5DIR | 04h |
| Port P5 pullup/pulldown enable | P5REN | 06h |
| Port P5 drive strength | P5DS | 08h |
| Port P5 selection | P5SEL | 0Ah |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| Port PJ input | PJIN | 00h |
| Port PJ output | PJOUT | 02h |
| Port PJ direction | PJDIR | 04h |
| Port PJ pullup/pulldown enable | PJREN | 06h |
| Port PJ drive strength | PJDS | 08h |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| TA0 control | TA0CTL | 00h |
| Capture/compare control 0 | TA0CCTL0 | 02h |
| Capture/compare control 1 | TA0CCTL1 | 04h |
| Capture/compare control 2 | TA0CCTL2 | 06h |
| Capture/compare control 3 | TA0CCTL3 | 08h |
| Capture/compare control 4 | TA0CCTL4 | 0Ah |
| TA0 counter | TA0R | 10h |
| Capture/compare 0 | TA0CCR0 | 12h |
| Capture/compare 1 | TA0CCR1 | 14h |
| Capture/compare 2 | TA0CCR2 | 16h |
| Capture/compare 3 | TA0CCR3 | 18h |
| Capture/compare 4 | TA0CCR4 | 1Ah |
| TA0 expansion 0 | TA0EX0 | 20h |
| TA0 interrupt vector | TA0IV | 2Eh |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| TA1 control | TA1CTL | 00h |
| Capture/compare control 0 | TA1CCTL0 | 02h |
| Capture/compare control 1 | TA1CCTL1 | 04h |
| Capture/compare control 2 | TA1CCTL2 | 06h |
| TA1 counter | TA1R | 10h |
| Capture/compare 0 | TA1CCR0 | 12h |
| Capture/compare 1 | TA1CCR1 | 14h |
| Capture/compare 2 | TA1CCR2 | 16h |
| TA1 expansion 0 | TA1EX0 | 20h |
| TA1 interrupt vector | TA1IV | 2Eh |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| RTC control 0 | RTCCTL0 | 00h |
| RTC control 1 | RTCCTL1 | 01h |
| RTC control 2 | RTCCTL2 | 02h |
| RTC control 3 | RTCCTL3 | 03h |
| RTC prescaler 0 control | RTCPS0CTL | 08h |
| RTC prescaler 1 control | RTCPS1CTL | 0Ah |
| RTC prescaler 0 | RTCPS0 | 0Ch |
| RTC prescaler 1 | RTCPS1 | 0Dh |
| RTC interrupt vector word | RTCIV | 0Eh |
| RTC seconds/counter 1 | RTCSEC/RTCNT1 | 10h |
| RTC minutes/counter 2 | RTCMIN/RTCNT2 | 11h |
| RTC hours/counter 3 | RTCHOUR/RTCNT3 | 12h |
| RTC day of week/counter 4 | RTCDOW/RTCNT4 | 13h |
| RTC days | RTCDAY | 14h |
| RTC month | RTCMON | 15h |
| RTC year low | RTCYEARL | 16h |
| RTC year high | RTCYEARH | 17h |
| RTC alarm minutes | RTCAMIN | 18h |
| RTC alarm hours | RTCAHOUR | 19h |
| RTC alarm day of week | RTCADOW | 1Ah |
| RTC alarm days | RTCADAY | 1Bh |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| 16-bit operand 1 – multiply | MPY | 00h |
| 16-bit operand 1 – signed multiply | MPYS | 02h |
| 16-bit operand 1 – multiply accumulate | MAC | 04h |
| 16-bit operand 1 – signed multiply accumulate | MACS | 06h |
| 16-bit operand 2 | OP2 | 08h |
| 16 × 16 result low word | RESLO | 0Ah |
| 16 × 16 result high word | RESHI | 0Ch |
| 16 × 16 sum extension | SUMEXT | 0Eh |
| 32-bit operand 1 – multiply low word | MPY32L | 10h |
| 32-bit operand 1 – multiply high word | MPY32H | 12h |
| 32-bit operand 1 – signed multiply low word | MPYS32L | 14h |
| 32-bit operand 1 – signed multiply high word | MPYS32H | 16h |
| 32-bit operand 1 – multiply accumulate low word | MAC32L | 18h |
| 32-bit operand 1 – multiply accumulate high word | MAC32H | 1Ah |
| 32-bit operand 1 – signed multiply accumulate low word | MACS32L | 1Ch |
| 32-bit operand 1 – signed multiply accumulate high word | MACS32H | 1Eh |
| 32-bit operand 2 – low word | OP2L | 20h |
| 32-bit operand 2 – high word | OP2H | 22h |
| 32 × 32 result 0 – least significant word | RES0 | 24h |
| 32 × 32 result 1 | RES1 | 26h |
| 32 × 32 result 2 | RES2 | 28h |
| 32 × 32 result 3 – most significant word | RES3 | 2Ah |
| MPY32 control 0 | MPY32CTL0 | 2Ch |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| DMA module control 0 | DMACTL0 | 00h |
| DMA module control 1 | DMACTL1 | 02h |
| DMA module control 2 | DMACTL2 | 04h |
| DMA module control 3 | DMACTL3 | 06h |
| DMA module control 4 | DMACTL4 | 08h |
| DMA interrupt vector | DMAIV | 0Ah |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| DMA channel 0 control | DMA0CTL | 00h |
| DMA channel 0 source address low | DMA0SAL | 02h |
| DMA channel 0 source address high | DMA0SAH | 04h |
| DMA channel 0 destination address low | DMA0DAL | 06h |
| DMA channel 0 destination address high | DMA0DAH | 08h |
| DMA channel 0 transfer size | DMA0SZ | 0Ah |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| DMA channel 1 control | DMA1CTL | 00h |
| DMA channel 1 source address low | DMA1SAL | 02h |
| DMA channel 1 source address high | DMA1SAH | 04h |
| DMA channel 1 destination address low | DMA1DAL | 06h |
| DMA channel 1 destination address high | DMA1DAH | 08h |
| DMA channel 1 transfer size | DMA1SZ | 0Ah |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| DMA channel 2 control | DMA2CTL | 00h |
| DMA channel 2 source address low | DMA2SAL | 02h |
| DMA channel 2 source address high | DMA2SAH | 04h |
| DMA channel 2 destination address low | DMA2DAL | 06h |
| DMA channel 2 destination address high | DMA2DAH | 08h |
| DMA channel 2 transfer size | DMA2SZ | 0Ah |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| USCI control 1 | UCA0CTL1 | 00h |
| USCI control 0 | UCA0CTL0 | 01h |
| USCI baud rate 0 | UCA0BR0 | 06h |
| USCI baud rate 1 | UCA0BR1 | 07h |
| USCI modulation control | UCA0MCTL | 08h |
| USCI status | UCA0STAT | 0Ah |
| USCI receive buffer | UCA0RXBUF | 0Ch |
| USCI transmit buffer | UCA0TXBUF | 0Eh |
| USCI LIN control | UCA0ABCTL | 10h |
| USCI IrDA transmit control | UCA0IRTCTL | 12h |
| USCI IrDA receive control | UCA0IRRCTL | 13h |
| USCI interrupt enable | UCA0IE | 1Ch |
| USCI interrupt flags | UCA0IFG | 1Dh |
| USCI interrupt vector word | UCA0IV | 1Eh |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| USCI synchronous control 1 | UCB0CTL1 | 00h |
| USCI synchronous control 0 | UCB0CTL0 | 01h |
| USCI synchronous bit rate 0 | UCB0BR0 | 06h |
| USCI synchronous bit rate 1 | UCB0BR1 | 07h |
| USCI synchronous status | UCB0STAT | 0Ah |
| USCI synchronous receive buffer | UCB0RXBUF | 0Ch |
| USCI synchronous transmit buffer | UCB0TXBUF | 0Eh |
| USCI I2C own address | UCB0I2COA | 10h |
| USCI I2C slave address | UCB0I2CSA | 12h |
| USCI interrupt enable | UCB0IE | 1Ch |
| USCI interrupt flags | UCB0IFG | 1Dh |
| USCI interrupt vector word | UCB0IV | 1Eh |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| Control 0 | ADC12CTL0 | 00h |
| Control 1 | ADC12CTL1 | 02h |
| Control 2 | ADC12CTL2 | 04h |
| Interrupt flag | ADC12IFG | 0Ah |
| Interrupt enable | ADC12IE | 0Ch |
| Interrupt vector word | ADC12IV | 0Eh |
| ADC memory-control 0 | ADC12MCTL0 | 10h |
| ADC memory-control 1 | ADC12MCTL1 | 11h |
| ADC memory-control 2 | ADC12MCTL2 | 12h |
| ADC memory-control 3 | ADC12MCTL3 | 13h |
| ADC memory-control 4 | ADC12MCTL4 | 14h |
| ADC memory-control 5 | ADC12MCTL5 | 15h |
| ADC memory-control 6 | ADC12MCTL6 | 16h |
| ADC memory-control 7 | ADC12MCTL7 | 17h |
| ADC memory-control 8 | ADC12MCTL8 | 18h |
| ADC memory-control 9 | ADC12MCTL9 | 19h |
| ADC memory-control 10 | ADC12MCTL10 | 1Ah |
| ADC memory-control 11 | ADC12MCTL11 | 1Bh |
| ADC memory-control 12 | ADC12MCTL12 | 1Ch |
| ADC memory-control 13 | ADC12MCTL13 | 1Dh |
| ADC memory-control 14 | ADC12MCTL14 | 1Eh |
| ADC memory-control 15 | ADC12MCTL15 | 1Fh |
| Conversion memory 0 | ADC12MEM0 | 20h |
| Conversion memory 1 | ADC12MEM1 | 22h |
| Conversion memory 2 | ADC12MEM2 | 24h |
| Conversion memory 3 | ADC12MEM3 | 26h |
| Conversion memory 4 | ADC12MEM4 | 28h |
| Conversion memory 5 | ADC12MEM5 | 2Ah |
| Conversion memory 6 | ADC12MEM6 | 2Ch |
| Conversion memory 7 | ADC12MEM7 | 2Eh |
| Conversion memory 8 | ADC12MEM8 | 30h |
| Conversion memory 9 | ADC12MEM9 | 32h |
| Conversion memory 10 | ADC12MEM10 | 34h |
| Conversion memory 11 | ADC12MEM11 | 36h |
| Conversion memory 12 | ADC12MEM12 | 38h |
| Conversion memory 13 | ADC12MEM13 | 3Ah |
| Conversion memory 14 | ADC12MEM14 | 3Ch |
| Conversion memory 15 | ADC12MEM15 | 3Eh |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| Comp_B control 0 | CBCTL0 | 00h |
| Comp_B control 1 | CBCTL1 | 02h |
| Comp_B control 2 | CBCTL2 | 04h |
| Comp_B control 3 | CBCTL3 | 06h |
| Comp_B interrupt | CBINT | 0Ch |
| Comp_B interrupt vector word | CBIV | 0Eh |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| AES accelerator control 0 | AESACTL0 | 00h |
| Reserved | 02h | |
| AES accelerator status | AESASTAT | 04h |
| AES accelerator key | AESAKEY | 06h |
| AES accelerator data in | AESADIN | 008h |
| AES accelerator data out | AESADOUT | 00Ah |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| LCD_B control 0 | LCDBCTL0 | 000h |
| LCD_B control 1 | LCDBCTL1 | 002h |
| LCD_B blinking control | LCDBBLKCTL | 004h |
| LCD_B memory control | LCDBMEMCTL | 006h |
| LCD_B voltage control | LCDBVCTL | 008h |
| LCD_B port control 0 | LCDBPCTL0 | 00Ah |
| LCD_B port control 1 | LCDBPCTL1 | 00Ch |
| LCD_B charge pump control | LCDBCTL0 | 012h |
| LCD_B interrupt vector word | LCDBIV | 01Eh |
| LCD_B memory 1 | LCDM1 | 020h |
| LCD_B memory 2 | LCDM2 | 021h |
| ... | ||
| LCD_B memory 14 | LCDM14 | 02Dh |
| LCD_B blinking memory 1 | LCDBM1 | 040h |
| LCD_B blinking memory 2 | LCDBM2 | 041h |
| ... | ||
| LCD_B blinking memory 14 | LCDBM14 | 04Dh |
| REGISTER DESCRIPTION | ACRONYM | OFFSET |
|---|---|---|
| Radio interface control 0 | RF1AIFCTL0 | 00h |
| Radio interface control 1 | RF1AIFCTL1 | 02h |
| Radio interface error flag | RF1AIFERR | 06h |
| Radio interface error vector word | RF1AIFERRV | 0Ch |
| Radio interface interrupt vector word | RF1AIFIV | 0Eh |
| Radio instruction word | RF1AINSTRW | 10h |
| Radio instruction word, 1-byte auto-read | RF1AINSTR1W | 12h |
| Radio instruction word, 2-byte auto-read | RF1AINSTR2W | 14h |
| Radio data in | RF1ADINW | 16h |
| Radio status word | RF1ASTATW | 20h |
| Radio status word, 1-byte auto-read | RF1ASTAT1W | 22h |
| Radio status word, 2-byte auto-read | RF1AISTAT2W | 24h |
| Radio data out | RF1ADOUTW | 28h |
| Radio data out, 1-byte auto-read | RF1ADOUT1W | 2Ah |
| Radio data out, 2-byte auto-read | RF1ADOUT2W | 2Ch |
| Radio core signal input | RF1AIN | 30h |
| Radio core interrupt flag | RF1AIFG | 32h |
| Radio core interrupt edge select | RF1AIES | 34h |
| Radio core interrupt enable | RF1AIE | 36h |
| Radio core interrupt vector word | RF1AIV | 38h |