ZHCSM58B January 2020 – November 2021 BQ76952
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information BQ76952
- 7.5 Supply Current
- 7.6 Digital I/O
- 7.7 LD Pin
- 7.8 Precharge (PCHG) and Predischarge (PDSG) FET Drive
- 7.9 FUSE Pin Functionality
- 7.10 REG18 LDO
- 7.11 REG0 Pre-regulator
- 7.12 REG1 LDO
- 7.13 REG2 LDO
- 7.14 Voltage References
- 7.15 Coulomb Counter
- 7.16 Coulomb Counter Digital Filter (CC1)
- 7.17 Current Measurement Digital Filter (CC2)
- 7.18 Current Wake Detector
- 7.19 Analog-to-Digital Converter
- 7.20 Cell Balancing
- 7.21 Cell Open Wire Detector
- 7.22 Internal Temperature Sensor
- 7.23 Thermistor Measurement
- 7.24 Internal Oscillators
- 7.25 High-side NFET Drivers
- 7.26 Comparator-Based Protection Subsystem
- 7.27 Timing Requirements - I2C Interface, 100kHz Mode
- 7.28 Timing Requirements - I2C Interface, 400kHz Mode
- 7.29 Timing Requirements - HDQ Interface
- 7.30 Timing Requirements - SPI Interface
- 7.31 Interface Timing Diagrams
- 7.32 Typical Characteristics
- 8 Device Description
- 9 Device Configuration
-
10Measurement Subsystem
- 10.1 Voltage Measurement
- 10.2 General Purpose ADCIN Functionality
- 10.3 Coulomb Counter and Digital Filters
- 10.4 Synchronized Voltage and Current Measurement
- 10.5 Internal Temperature Measurement
- 10.6 Thermistor Temperature Measurement
- 10.7 Factory Trim of Voltage ADC
- 10.8 Voltage Calibration (ADC Measurements)
- 10.9 Voltage Calibration (COV and CUV Protections)
- 10.10 Current Calibration
- 10.11 Temperature Calibration
- 11Primary and Secondary Protection Subsystems
-
12Device
Hardware Features
- 12.1 Voltage References
- 12.2 ADC Multiplexer
- 12.3 LDOs
- 12.4 Standalone Versus Host Interface
- 12.5 Multifunction Pin Controls
- 12.6 RST_SHUT Pin Operation
- 12.7 CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
- 12.8 ALERT Pin Operation
- 12.9 DDSG and DCHG Pin Operation
- 12.10 Fuse Drive
- 12.11 Cell Open Wire
- 12.12 Low Frequency Oscillator
- 12.13 High Frequency Oscillator
- 13Device Functional Modes
- 14Serial Communications Interface
- 15Cell Balancing
- 16Application and Implementation
- 17Power Supply Requirements
- 18Layout
- 19Device and Documentation Support
- 20Mechanical, Packaging, Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PFB|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
16.4 Startup Timing
At initial power up of the BQ76952 device from a SHUTDOWN state, the device progresses through a sequence of events before entering NORMAL mode operation. These are described below for an example configuration, with approximate timing shown for the cases when [FASTADC] = 0 and [FASTADC] = 1.
Note: When the device is configured for
autonomous FET control (that is, [FET_EN] = 1), the decision to enable
FETs is only evaluated every 250 ms while in NORMAL mode, which is why the FETs are
not enabled until approximately 280 ms after the wakeup event, even though the data
was available earlier.
Table 16-2 Startup Sequence and
Timing
| Step | Comment | FASTADC Setting | Time (relative to wakeup event) |
|---|---|---|---|
| Wakeup event | Either the TS2 pin is pulled low, or the LD pin is pulled up, triggering the device to exit SHUTDOWN mode. | 0, 1 | 0 |
| REG1 powered | This was measured with the OTP programmed to autonomously power the REG1 LDO. | 0, 1 | 20 ms |
| INITSTART asserted | This was measured with the OTP programmed to provide the INITSTART bit in the Alarm signal on the ALERT pin. | 0, 1 | 23 ms |
| INITCOMP and ADSCAN asserted | This was measured with the OTP programmed to provide the INITCOMP and ADSCAN bits in the Alarm signal on the ALERT pin. | 0 | 88 ms |
| 1 | 58 ms | ||
| FULLSCAN asserted | This was measured with the OTP programmed to provide the FULLSCAN bit in the Alarm signal on the ALERT pin. | 0 | 221 ms |
| 1 | 129 ms | ||
| FETs enabled | This was measured with the OTP programmed to autonomously enable FETs. | 0 | 282 ms |
| 1 | 284 ms |
Figure 16-5 shows an example of an oscilloscope plot of a startup sequence with the device configured in OTP with [FASTADC] = 1, [FET_EN] = 1 for autonomous FET control, setup to use three thermistors, and providing the [INITCOMP] flag on the ALERT pin. The TS2 pin is pulled low to initiate device wakeup from SHUTDOWN.
Figure 16-5 Startup Sequence Using [FASTADC] = 1, with the [INITCOMP] Flag Displayed on the ALERT Pin