ZHCSCE2I October 2013 – March 2022 BQ76920 , BQ76930 , BQ76940
PRODMIX
| PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY CURRENTS | ||||||
| IDD | NORMAL mode: ADC off, CC off | Sum of ICC_BAT and ICC_REGSRC currents | 40 | 60 | μA | |
| NORMAL mode: ADC on, CC off | 60 | 90 | ||||
| NORMAL mode: ADC off, CC on | 110 | 165 | ||||
| NORMAL mode: ADC on, CC on | 130 | 195 | ||||
| ICC_BAT | NORMAL mode: ADC off | Into BAT pin | 30 | 45 | ||
| NORMAL mode: ADC on | 50 | 75 | ||||
| ICC_REGSRC | NORMAL mode: CC off | Into REGSRC pin | 10 | 15 | ||
| NORMAL mode: CC on | 80 | 120 | ||||
| ISHIP | SHIP/SHUTDOWN mode | Device in full shutdown, only VSTUP/BG and BOOT detector on | 0.6 | 1.8 | ||
| LEAKAGE AND OFFSET CURRENTS | ||||||
| dINOM | NORMAL mode supply current offset | Measured into VC5x (BQ76930, BQ76940) and VC10x (BQ76940) | –5 | ±2.5 | 5 | μA |
| dISHIP | SHIP mode supply current offset | –1.0 | ±0.1 | 1.0 | ||
| dIALERT | Supply current when ALERT active | Measured into VC5x (BQ76930, BQ76940) or added to BAT (BQ76920) | 15 | 25 | ||
| dICELL | Cell measurement input current | Measured into VC0–VC15 except VC5, VC10, VC15 | –0.3 | ±0.1 | 0.3 | |
| Measured into VC5, VC10, VC15 | 0.5 | |||||
| ILKG | Terminal input leakage | 1 | ||||
| INTERNAL POWER CONTROL (STARTUP and SHUTDOWN) | ||||||
| VPORA | Analog POR threshold | VBAT rising. See (4). | 4 | 5 | V | |
| VSHUT | Shutdown voltage | VBAT falling. See (4). | 3.6 | V | ||
| tI2CSTARTUP | Time delay after boot signal on TS1 before I2C communications allowed | Delay after boot sequence when I2C communication is allowed | 1 | ms | ||
| tBOOTREADY | Device boot startup delay | Delay after boot signal when device has completed full boot-up sequence | 10 | ms | ||
| TSHUTD | Thermal shutdown voltage | 100 | 150 | °C | ||
| MEASUREMENT SCHEDULE | ||||||
| tVCELL | Cell voltage measurement interval | BQ76920, BQ76930, BQ76940 | 250 | ms | ||
| tINDCELL | Individual cell measurement time | Per cell, balancing off | 50 | |||
| Per cell, balancing on | 12.5 | |||||
| tCB_RELAX | Cell balancing relaxation time before cell voltage measured | 12.5 | ||||
| tTEMP_DEC | Temperature measurement decimation time | Measurement duration for temperature reading | 12.5 | |||
| tBAT | Pack voltage calculation interval | 250 | ||||
| tTEMP | Temperature measurement interval | Period of measurement of either TS1/TS2/TS3 or internal die temp | 2 | s | ||
| 14-BIT ADC FOR CELL VOLTAGE AND TEMPERATURE MEASUREMENT | ||||||
| ADCRANGE | ADC measurement recommend operation range | VCELL measurements | 2 | 5 | V | |
| TS/Temp measurements | 0.3 | 3 | V | |||
| ADCLSB | ADC LSB value | 382 | μV | |||
| ADC | ADC cell voltage accuracy at 25°C | VCELL = 3.6 V – 4.3 V | ±10 | mV | ||
| VCELL = 3.2 V – 4.6 V | ±15 | |||||
| VCELL = 2.0 V – 5.0 V | ±25 | |||||
| ADC cell voltage accuracy 0°C to 60°C | VCELL = 3.6 V – 4.3 V | ±20 | ||||
| VCELL = 3.2 V – 4.6 V | ±25 | |||||
| VCELL = 2.0 V – 5.0 V | ±35 | |||||
| ADC cell voltage accuracy –40°C to 85°C | VCELL = 3.6 V – 4.3 V | –40 | 40 | |||
| VCELL = 3.2 V – 4.6 V | –40 | 40 | ||||
| VCELL = 2.0 V – 5.0 V | –50 | 50 | ||||
| 16-BIT CC FOR PACK CURRENT MEASUREMENT | ||||||
| CCRANGE | CC input voltage range | –200 | 200 | mV | ||
| CCFSR | CC full scale range | –270 | 270 | mV | ||
| CCLSB | CC LSB value | CC running constantly | 8.44 | μV | ||
| tCCREAD | Conversion time | Single conversion | 250 | ms | ||
| CCINL | Integral nonlinearity | 16-bit, best fit over input voltage range ± 200 mV | ± 2 | ± 40 | LSB | |
| CCOFFSET | Offset error | ± 1 | ± 3 | LSB | ||
| CCGAIN | Gain error | Over input voltage range | ± 0.5% | ± 1.5% | FSR | |
| CCGAINDRIFT | Gain error drift | Over input voltage range | 150 | PPM / °C | ||
| CCRIN | Effective input resistance | 2.5 | MΩ | |||
| THERMISTOR BIAS | ||||||
| RTS | Pull-up resistance | TA = 25°C | 9.85 | 10 | 10.15 | kΩ |
| RTSDRIFT | Pull-up resistance across temp | TA = –40°C to 85°C | 9.7 | 10.3 | kΩ | |
| DIETEMP | ||||||
| VDIETEMP25 | Die temperature voltage | TA = 25°C | 1.20 | V | ||
| VDIETEMPDRIFT | Die temperature voltage drift | –4.2 | mV/°C | |||
| INTEGRATED HARDWARE PROTECTIONS | ||||||
| OVRANGE | OV threshold range | 0x2008 | 0x2FF8 | ADC | ||
| UVRANGE | UV threshold range | 0x1000 | 0x1FF0 | ADC | ||
| OVUVSTEP | OV and UV threshold step size | 16 | LSB | |||
| UVMINQUAL | UV minimum value to qualify | Below UVMINQUAL, the cell is shorted (unused) | 0x0518 | ADC | ||
| OVDELAY | OV delay timer options | OV delay = 1 s | 0.7 | 1 | 1.75 | s |
| OV delay = 2 s | 1.6 | 2 | 2.75 | |||
| OV delay = 4 s | 3.5 | 4 | 5 | |||
| OV delay = 8 s | 7 | 8 | 10 | |||
| UVDELAY | UV delay timer options | UV delay = 1 s | 0.7 | 1 | 1.75 | |
| UV delay = 4 s | 3.5 | 4 | 5 | |||
| UV delay = 8 s | 7 | 8 | 10 | |||
| UV delay = 16 s | 14 | 16 | 20 | |||
| OCDRANGE | OCD threshold options | Measured across (SRP–SRN)(2) | 8 | 100 | mV | |
| OCDSTEP | OCD threshold step size | RSNS = 0 | 2.78 | mV | ||
| RSNS = 1 | 5.56 | mV | ||||
| OCDDELAY | OCD delay options | See Note(3) | 8 | 1280 | ms | |
| SCDRANGE | SCD threshold options | Measured across (SRP–SRN)(2) | 22 | 200 | mV | |
| SCDSTEP | SCD threshold step size | RSNS = 0 | 11.1 | mV | ||
| RSNS = 1 | 22.2 | mV | ||||
| SCDDELAY | SCD delay options | 35 | 70 | 105 | μs | |
| 50 | 100 | 150 | μs | |||
| 140 | 200 | 260 | μs | |||
| 280 | 400 | 520 | μs | |||
| tPROTACC | Delay accuracy for OCD | –20% | 20% | |||
| OCOFFSET | OCD and SCD voltage offset | –2.5 | 2.5 | mV | ||
| OCSCALEERR | OCD and SCD scale accuracy | –10% | 10% | |||
| CHARGE AND DISCHARGE DRIVERS | ||||||
| VFETON | CHG and DSG on | REGSRC ≥ 12 V with load resistance of 10 MΩ | 10 | 12 | 14 | V |
| REGSRC < 12 V with load resistance of 10 MΩ | REGSRC –2 | REGSRC –1 | REGSRC | V | ||
| tFET_ON | CHG and DSG ON rise time | CHG/DSG driving an equivalent load capacitance of 10 nF, measured from 10% to 90% of VFETON | 200 | 250 | μs | |
| tDSG_OFF | DSG pull-down OFF fall time | DSG driving an equivalent load capacitance of 10 nF, measured from 90% to 10% | 60 | 90 | μs | |
| RCHG_OFF | CHG pull-down OFF resistance to VSS | When CHG disabled, CHG held at 12 V | 750 | 1000 | 1250 | kΩ |
| RDSG_OFF | DSG pull-down OFF resistance to VSS | When DSG disabled, DSG held at 12 V | 1.75 | 2.50 | 4.25 | kΩ |
| VLOAD_DETECT | Load detection threshold | 0.4 | 0.7 | 1.0 | V | |
| VCHG_CLAMP | CHG clamp voltage | If the CHG pin externally pulled high (through PACK–, if load applied), 500-μA max sink current into CHG pin. With CHG_ON bit cleared. | 18 | 20 | 22 | V |
| ALERT PIN | ||||||
| VALERT_OH | ALERT output voltage high | IOL = 1 mA | REGOUT x 0.75 | V | ||
| VALERT_OL | ALERT output voltage low | Unloaded | REGOUT x 0.25 | V | ||
| VALERT_IH | ALERT input high | ALERT externally forced high when internally driven low. See note (1). | 1 | 1.5 | V | |
| RALERT_PD | ALERT pin weak pulldown resistance when driven low | Measured into ALERT pin with ALERT = REGOUT | 0.8 | 2.5 | 8 | MΩ |
| CELL BALANCING DRIVER | ||||||
| RDSFET | Internal cell balancing driver resistance | VCELL = 3.6 V | 1 | 5 | 10 | Ω |
| XBAL | Cell balancing duty cycle when enabled | Every 250 ms | 70% | |||
| EXTERNAL REGULATOR | ||||||
| VEXTLDO | External LDO voltage options | Nominal values, TI factory programmed, unloaded, across temp | 2.45 | 2.50 | 2.55 | V |
| 3.20 | 3.30 | 3.40 | V | |||
| VEXTLDO_LN | Line regulation | REGSRC pin stepped from 6 to 25 V, with 10-mA load, in 100 μs | 100 | mV | ||
| VEXTLDO_LD | Load regulation | IREGOUT = 0 mA to 10 mA | –4% | 4% | ||
| VEXTLDO_DC | External LDO minimum voltage under DC load | REGOUT = 10-mA DC, 2.5-V version | 2.4 | V | ||
| REGOUT = 20-mA DC, 2.5-V version | 2.3 | V | ||||
| REGOUT = 10-mA DC, 3.3-V version | 3.15 | V | ||||
| REGOUT = 20-mA DC, 3.3-V version | 3.05 | V | ||||
| IEXTLDO_LIMIT | External LDO current limit | REGOUT = 0 V | 30 | 38 | 45 | mA |
| BOOT DETECTOR | ||||||
| VBOOT | Boot threshold voltage | Measured at TS1 pin with device in SHIP mode. Below MIN, the device does not boot up. Above MAX, the device boots up. | 300 | 1000 | mV | |
| tBOOT_max | Boot threshold application time | Measured at TS1 pin. Below MIN, the device does not boot up. Above MAX, the device boots up. | 10 | 2000 | μs | |