Each BQ769x0 device measures cell voltages and temperatures using a 14-bit ADC. This ADC measures all differential cell voltages, thermistors and/or die temperature with a nominal full-scale unsigned range of 0–6.275 V and LSB of 382 μV.

To enable the ADC, the [ADC_EN] bit in the SYS_CTRL1 register must be set. This bit is set automatically whenever the device enters NORMAL mode. When enabled, the ADC ensures that the integrated OV and UV protections are functional.

For each contiguous set of five cells (VC1 to VC5, VC6 to VC10), when no cells in that particular set are being balanced, each cell is measured over a 50-ms decimation window and a complete update is available every 250 ms. In the BQ76930 and BQ76940, every set of five cells above the primary five cells is measured in parallel. The 50-ms decimation greatly assists with removing the aliasing effects present in a noisy motor environment.

When any cells in a contiguous set of 5 cells are being balanced, those affected cells are measured in a reduced 12.5-ms decimation period, to allow the cell balancing to function properly without affecting the integrated OV and UV protections. Since cell balancing is typically only performed during pack charge or idle periods, the shortened decimation periods should not impact accuracy as the system noise during these times is greatly reduced. This reduced decimation period is only applied to sets where one of the cells is being balanced. The following summarizes this for the BQ76920–BQ76940 devices:

• VC1 to VC5 measurements are each taken in a 50-ms decimation period when all bits in CELLBAL1 register are 0, and a 12.5-ms decimation period when any bits in CELLBAL1 register are 1.
• VC6 to VC10 measurements are each taken in a 50-ms decimation period when all bits in CELLBAL2 register are 0, and a 12.5-ms decimation period when any bits in CELLBAL2 register are 1.
• VC11 to VC15 measurements are each taken in a 50-ms decimation period when all bits in CELLBAL3 register are 0, and a 12.5-ms decimation period when any bits in CELLBAL3 register are 1.
• Total update interval is 250 ms.

Each differential cell input is factory-trimmed for gain or offset, such that the resulting reading through I²C is always consistent from part-to-part and requires no additional calibration or correction factor application.

The ADC is required to be enabled in order for the integrated OV and UV protections to be operating.

The following shows how to convert the 14-bit ADC reading into an analog voltage. Each device is factory calibrated, with a GAIN and OFFSET stored into EEPROM.

The ADC transfer function is a linear equation defined as follows:

GAIN is stored in units of μV/LSB, while OFFSET is stored in mV units.

Some example cell voltage calculations are provided in the table below. For illustration purposes, the example uses a hypothetical GAIN of 380 μV/LSB (ADCGAIN<4:0> = 0x0F) and OFFSET of 30 mV (ADCOFFSET<7:0> = 0x1E).