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ZHCSCE2I October 2013 – March 2022 BQ76920 , BQ76930 , BQ76940

PRODMIX

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DBT|44
- MPDS350B

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

8.5.1 Register Details

Table 8-3 SYS_STAT (0x00)

BIT	7	6	5	4	3	2	1	0
NAME	CC_READY	RSVD	DEVICE_ XREADY	OVRD_ ALERT	UV	OV	SCD	OCD
RESET	0	0	0	0	0	0	0	0
ACCESS	RW	RW	RW	RW	RW	RW	RW	RW

Note:

Bits in SYS_STAT may be cleared by writing a "1" to the corresponding bit.

Writing a "0" does not change the state of the corresponding bit.

CC_READY (Bit 7): Indicates that a fresh coulomb counter reading is available. Note that if this bit is not cleared between two adjacent CC readings becoming available, the bit remains latched to 1. This bit may only be cleared (and not set) by the host.
	0 =	Fresh CC reading not yet available or bit is cleared by host microcontroller.
	1 =	Fresh CC reading is available. Remains latched high until cleared by host.

RSVD (Bit 6): Reserved. Do not use.

DEVICE_XREADY (Bit 5): Internal chip fault indicator. When this bit is set to 1, it should be cleared by the host. May be set due to excessive system transients. This bit may only be cleared (and not set) by the host.
	0 =	Device is OK.
	1 =	Internal chip fault detected, recommend that host microcontroller clear this bit after waiting a few seconds. Remains latched high until cleared by the host.

OVRD_ALERT (Bit 4): External pull-up on the ALERT pin indicator. Only active when ALERT pin is not already being driven high by the AFE itself.
	0 =	No external override detected
	1 =	External override detected. Remains latched high until cleared by the host.

UV (Bit 3): Undervoltage fault event indicator.
	0 =	No UV fault is detected.
	1 =	UV fault is detected. Remains latched high until cleared by the host.

OV (Bit 2): Overvoltage fault event indicator.
	0 =	No OV fault is detected.
	1 =	OV fault is detected. Remains latched high until cleared by the host.

SCD (Bit 1): Short circuit in discharge fault event indicator.
	0 =	No SCD fault is detected.
	1 =	SCD fault is detected. Remains latched high until cleared by the host.

OCD (Bit 0): Over current in discharge fault event indicator.
	0 =	No OCD fault is detected.
	1 =	OCD fault is detected. Remains latched high until cleared by the host.

Table 8-4 CELLBAL1 (0x01) for BQ76920, BQ76930, and BQ76940

BIT	7	6	5	4	3	2	1	0
NAME	—	—	—	CB5	CB4	CB3	CB2	CB1
RESET	0	0	0	0	0	0	0	0
ACCESS	R	R	R	RW	RW	RW	RW	RW

CBx (Bits 4–0):
	0 =	Cell balancing on Cell “x” is disabled.
	1 =	Cell balancing on Cell “x” is enabled.

Table 8-5 CELLBAL2 (0x02) for BQ76930 and BQ76940

BIT	7	6	5	4	3	2	1	0
NAME	—	—	—	CB10	CB9	CB8	CB7	CB6
RESET	0	0	0	0	0	0	0	0
ACCESS	R	R	R	RW	RW	RW	RW	RW


CBx (Bits 4–0):
	0 =	Cell balancing on Cell “x” is disabled.
	1 =	Cell balancing on Cell “x” is enabled.

Table 8-6 CELLBAL3 (0x03) for BQ76940

BIT	7	6	5	4	3	2	1	0
NAME	—	—	—	CB15	CB14	CB13	CB12	CB11
RESET	0	0	0	0	0	0	0	0
ACCESS	R	R	R	RW	RW	RW	RW	RW


CBx (Bits 4–0):
	0 =	Cell balancing on Cell “x” is disabled.
	1 =	Cell balancing on Cell “x” is enabled.

Table 8-7 SYS_CTRL1 (0x04)

BIT	7	6	5	4	3	2	1	0
NAME	LOAD_ PRESENT	—	—	ADC_EN	TEMP_SEL	RSVD	SHUT_A	SHUT_B
RESET	0	0	0	0	0	0	0	0
ACCESS	R	R	R	RW	RW	RW	RW	RW


LOAD_PRESENT (Bit 7): Valid only when [CHG_ON] = 0. Is high if CHG pin is detected to exceed VLOAD_DETECT while CHG_ON = 0, which suggests that external load is present. Note this bit is read-only and automatically clears when load is removed.
	0 =	CHG pin < VLOAD_DETECT or [CHG_ON] = 1.
	1 =	CHG pin >VLOAD_DETECT, while [CHG_ON] = 0.

ADC_EN (Bit 4): ADC enable command
	0 =	Disable voltage and temperature ADC readings (also disables OV protection)
	1 =	Enable voltage and temperature ADC readings (also enables OV protection)

TEMP_SEL (Bit 3): TSx_HI and TSx_LO temperature source
	0 =	Store internal die temperature voltage reading in TSx_HI and TSx_LO
	1 =	Store thermistor reading in TSx_HI and TSx_LO (all thermistor ports)

RSVD (Bit 2): Reserved, do not set to 1.

SHUT_A, SHUT_B (Bits 1–0): Shutdown command from host microcontroller. Must be written in a specific sequence, shown below:
Starting from: [SHUT_A] = 0, [SHUT_B] = 0
		Write #1: [SHUT_A] = 0, [SHUT_B] = 1
		Write #2: [SHUT_A] = 1, [SHUT_B] = 0
Other writes cause the command to be ignored.

Table 8-8 SYS_CTRL2 (0x05)

BIT	7	6	5	4	3	2	1	0
NAME	DELAY_DIS	CC_EN	CC_ ONESHOT	RSVD	RSVD	RSVD	DSG_ON	CHG_ON
RESET	0	0	0	0	0	0	0	0
ACCESS	RW	RW	RW	RW	RW	RW	RW	RW


DELAY_DIS (Bit 7): Disable OV, UV, OCD, and SCD delays for faster customer production testing.
	0 =	Normal delay settings
	1 =	OV, UV, OCD, and SCD delay circuit is bypassed, creating zero delay (approximately 250 ms).

CC_EN (Bit 6): Coulomb counter continuous operation enable command. If set high, [CC_ONESHOT] bit is ignored.
	0 =	Disable CC continuous readings
	1 =	Enable CC continuous readings and ignore [CC_ONESHOT] state

CC_ONESHOT (Bit 5): Coulomb counter single 250-ms reading trigger command. If set to 1, the coulomb counter will be activated for a single 250-ms reading, and then turned back off. [CC_ONESHOT] will also be cleared at the conclusion of this reading, while [CC_READY] bit will be set to 1.
	0 =	No action
	1 =	Enable single CC reading (only valid if [CC_EN] = 0), and [CC_READY] = 0)

RSVD (Bits 4–2): Reserved. Do not use.

DSG_ON (Bit 1): Discharge FET driver (low side NCH) or discharge signal control
	0 =	DSG is off.
	1 =	DSG is on.

CHG_ON (Bit 0): Discharge FET driver (low side NCH) or discharge signal control
	0 =	CHG is off.
	1 =	CHG is on.

Table 8-9 PROTECT1 (0x06)

BIT	7	6	5	4	3	2	1	0
NAME	RSNS	—	RSVD	SCD_D1	SCD_D0	SCD_T2	SCD_T1	SCD_T0
RESET	0	0	0	0	0	0	0	0
ACCESS	RW	R	RW	RW	RW	RW	RW	RW


RSNS (Bit 7): Allows for doubling the OCD and SCD thresholds simultaneously
	0 =	OCD and SCD thresholds at lower input range
	1 =	OCD and SCD thresholds at upper input range

RSVD (Bit 5): Reserved, do not set to 1.

SCD_D1:0 (Bits 4–3): Short circuit in discharge delay setting. A 400-μs setting is recommended only in systems using maximum cell measurement input resistance, Rc, of 1 kΩ (which corresponds to minimum internal cell balancing current or external cell balancing configuration).

Code	(in μs)
0x0	70
0x1	100
0x2	200
0x3	400


SCD_T2:0 (Bits 2–0): Short circuit in discharge threshold setting

Code	RSNS = 1 (in mV)	RSNS = 0 (in mV)
0x0	44	22
0x1	67	33
0x2	89	44
0x3	111	56
0x4	133	67
0x5	155	78
0x6	178	89
0x7	200	100

Table 8-10 PROTECT2 (0x07)

BIT	7	6	5	4	3	2	1	0
NAME	—	OCD_D2	OCD_D1	OCD_D0	OCD_T3	OCD_T2	OCD_T1	OCD_T0
RESET	0	0	0	0	0	0	0	0
ACCESS	R	RW	RW	RW	RW	RW	RW	RW


OCD_D2:0 (Bits 6–4): Overcurrent in discharge delay setting

Code	(in ms)
0x0	8
0x1	20
0x2	40
0x3	80
0x4	160
0x5	320
0x6	640
0x7	1280


OCD_T3:0 (Bits 3–0): Overcurrent in discharge threshold setting

Code	RSNS = 1 (in mV)	(RSNS = 0 (in mV)
0x0	17	8
0x1	22	11
0x2	28	14
0x3	33	17
0x4	39	19
0x5	44	22
0x6	50	25
0x7	56	28
0x8	61	31
0x9	67	33
0xA	72	36
0xB	78	39
0xC	83	42
0xD	89	44
0xE	94	47
0xF	100	50

Table 8-11 PROTECT3 (0x08)

BIT	7	6	5	4	3	2	1	0
NAME	UV_D1	UV_D0	OV_D1	OV_D0	RSVD	RSVD	RSVD	RSVD
RESET	0	0	0	0	0	0	0	0
ACCESS	RW	RW	RW	RW	RW	RW	RW	RW


UV_D1:0 (Bits 7–6): Undervoltage delay setting

Code	(in s)
0x0	1
0x1	4
0x2	8
0x3	16


OV_D1:0 (Bits 5–4): Overvoltage delay setting

Code	(in s)
0x0	1
0x1	2
0x2	4
0x3	8


RSVD (Bits 3–0): These bits are for TI internal debug use only and must be configured to the default settings indicated.

Table 8-12 OV_TRIP (0x09)

BIT	7	6	5	4	3	2	1	0
NAME	OV_T7	OV_T6	OV_T5	OV_T4	OV_T3	OV_T2	OV_T1	OV_T0
RESET	1	0	1	0	1	1	0	0
ACCESS	RW	RW	RW	RW	RW	RW	RW	RW


OV_T7:0 (Bits 7–0): Middle 8 bits of the direct ADC mapping of the desired OV protection threshold, with upper 2 MSB set to 10 and lower 4 LSB set to 1000. The equivalent OV threshold is mapped to: 10-OV_T<7:0>1000.

By default, OV_TRIP is configured to a 0xAC setting.

Note that OV_TRIP is based on the ADC voltage, which requires back-calculation using the GAIN and OFFSET values stored in ADCGAIN<4:0>and ADCOFFSET<7:0>.

Table 8-13 UV_TRIP (0x0A)

BIT	7	6	5	4	3	2	1	0
NAME	UV_T7	UV_T6	UV_T5	UV_T4	UV_T3	UV_T2	UV_T1	UV_T0
RESET	1	0	0	1	0	1	1	1
ACCESS	RW	RW	RW	RW	RW	RW	RW	RW


UV_T7:0 (Bits 7–0): Middle 8 bits of the direct ADC mapping of the desired UV protection threshold, with upper 2 MSB set to 01 and lower 4 LSB set to 0000. In other words, the equivalent OV threshold is mapped to: 01-UV_T<7:0>–0000.

By default, UV_TRIP is configured to a 0x97 setting.

Note that UV_TRIP is based on the ADC voltage, which requires back-calculation using the GAIN and OFFSET values stored in ADCGAIN<4:0>and ADCOFFSET<7:0>.

Table 8-14 CC_CFG REGISTER (0x0B)

BIT	7	6	5	4	3	2	1	0
NAME	—	—	CC_CFG5	CC_CFG4	CC_CFG3	CC_CFG2	CC_CFG1	CC_CFG0
RESET	0	0	0	0	0	0	0	0
ACCESS	R	R	RW	RW	RW	RW	RW	RW


CC_CFG5:0 (Bits 5–0): For optimal performance, these bits should be programmed to 0x19 upon device startup.

Code	RSNS = 1 (in mV)	RSNS = 0 (in mV)
0x0	44	22
0x1	67	33
0x2	89	44
0x3	111	56
0x4	133	67
0x5	155	78
0x6	178	89
0x7	200	100

Code	RSNS = 1 (in mV)	(RSNS = 0 (in mV)
0x0	17	8
0x1	22	11
0x2	28	14
0x3	33	17
0x4	39	19
0x5	44	22
0x6	50	25
0x7	56	28
0x8	61	31
0x9	67	33
0xA	72	36
0xB	78	39
0xC	83	42
0xD	89	44
0xE	94	47
0xF	100	50

Code	RSNS = 1 (in mV)	RSNS = 0 (in mV)
0x0	44	22
0x1	67	33
0x2	89	44
0x3	111	56
0x4	133	67
0x5	155	78
0x6	178	89
0x7	200	100

Code	RSNS = 1 (in mV)	(RSNS = 0 (in mV)
0x0	17	8
0x1	22	11
0x2	28	14
0x3	33	17
0x4	39	19
0x5	44	22
0x6	50	25
0x7	56	28
0x8	61	31
0x9	67	33
0xA	72	36
0xB	78	39
0xC	83	42
0xD	89	44
0xE	94	47
0xF	100	50

Code	RSNS = 1 (in mV)	RSNS = 0 (in mV)
0x0	44	22
0x1	67	33
0x2	89	44
0x3	111	56
0x4	133	67
0x5	155	78
0x6	178	89
0x7	200	100

Code	RSNS = 1 (in mV)	(RSNS = 0 (in mV)
0x0	17	8
0x1	22	11
0x2	28	14
0x3	33	17
0x4	39	19
0x5	44	22
0x6	50	25
0x7	56	28
0x8	61	31
0x9	67	33
0xA	72	36
0xB	78	39
0xC	83	42
0xD	89	44
0xE	94	47
0xF	100	50